UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 715

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.7.2 LIN reception
78K0R/KG3-L support LIN communication.
Notes 1. 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: UART0
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. f
Of UART reception, UART0 of the 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L and UART3 of the 78K0R/KF3-L,
The following UART channels are used for LIN reception.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: Channel 1 of SAU0
78K0R/KF3-L, 78K0R/KG3-L:
Figure 14-94 outlines a reception operation of LIN.
Support of LIN communication
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
2. UART4 is only mounted in the 78K0R/KF3-L (
3. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
78K0R/KF3-L, 78K0R/KG3-L:
78F1030).
specifications (see CHAPTER 30
78K0R/KE3-L), CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
2. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3)
f
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 01
78K0R/KF3-L, 78K0R/KG3-L:
MCK
CLK
UART
:
:
Operation clock frequency of target channel
System clock frequency
Supported
Channel 1 of
SAU0
RxD0
INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
INTSRE0
• Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (The parity bit is not checked.)
• Appending 0 parity (The parity bit is not checked.)
• Even-parity check
• Odd-parity check
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
UART0
MCK
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
Note 1
Channel 3 of SAU1
Not supported
ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L,
UART1
UART3
−
−
−
−
μ
mn = 13
PD78F1027, 78F1028) and 78K0R/KG3-L (
Not supported
UART2
−
−
−
−
CHAPTER 14 SERIAL ARRAY UNIT
CLK
/(2 × 2
Supported
Channel 3 of
SAU1
RxD3
INTSR3
11
UART3
INTSRE3
× 128) [bps]
Note 1
Note 3
Not supported
UART4
μ
PD78F1029,
−
−
−
Note 2
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