UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 792

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.5.14 Communication reservation
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register (IICF) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is
not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If bit 1 (STT) of the IICCTL0 register is set to 1 while the bus is not used (after a stop condition is detected), a start
condition is automatically generated and wait state is set.
If an address is written to the IICA shift register (IICA) after bit 4 (SPIE) of the IICCTL0 register was set to 1, and it
was detected by generation of an interrupt request signal (INTIICA) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to the IICA register
before the stop condition is detected is invalid.
When the STT bit has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using the MSTS bit (bit 7 of the IICA status
register (IICS)) after the STT bit is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
released by setting bit 6 (LREL) of IICA control register 0 (IICCTL0) to 1 and saving communication).
Remark IICWL: IICA low-level width setting register
Wait time from setting STT = 1 to checking the MSTS flag:
(IICWL setting value + IICWH setting value + 4) + t
IICWH: IICA high-level width setting register
t
f
F
CLK
:
:
SDA0 and SCL0 signal falling times
CPU/peripheral hardware clock frequency
F
× 2 × f
CLK
CHAPTER 15 SERIAL INTERFACE IICA
[clocks]
792