UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 598

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
SMRmn
(4) Serial communication operation setting register mn (SCRmn)
Symbol
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit,
start bit, stop bit, and data length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
Remark m: Unit number (m = 0 to 2), n : Channel number (n = 0 to 3)
F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13),
F0208H, F0209H (SMR20), F020AH, F020BH (SMR21)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has
run out.
CKS
mn0
mn2
mn0
SIS
MD
MD
mn
15
0
1
0
0
1
1
0
1
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L
78K0R/KF3-L
78K0R/KG3-L
78K0R/KG3-L
Falling edge is detected as the start bit.
The input communication data is captured as is.
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
Transfer end interrupt
Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
CCS
mn1
MD
mn
14
0
1
0
1
CSI mode
UART mode
Simplified I
Setting prohibited
Figure 14-7. Format of Serial Mode Register mn (SMRmn) (3/3)
13
0
μ
μ
μ
μ
12
0
PD78F1010, 78F1011, 78F1012 : mn = 00 to 03, 10 to 13
PD78F1027, 78F1028 :
PD78F1013, 78F1014 :
PD78F1029, 78F1030 :
2
C mode
Controls inversion of level of receive data of channel n in UART mode
11
0
10
0
Selection of interrupt source of channel n
Setting of operation mode of channel n
9
0
STS
mn
8
After reset: 0020H
7
0
mn = 00 to 03
mn = 00 to 03, 10 to 13, 20, 21
mn = 00 to 03, 10 to 13
mn = 00 to 03, 10 to 13, 20, 21
mn0
SIS
6
CHAPTER 14 SERIAL ARRAY UNIT
5
1
R/W
4
0
3
0
mn2
MD
2
mn1
MD
1
mn0
MD
0
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