DS3163 Maxim Integrated Products, DS3163 Datasheet
DS3163
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DS3163 Summary of contents
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... GENERAL DESCRIPTION The DS3161, DS3162, DS3163, and DS3164 (DS316x) integrate ATM processor(s) with DS3/E3 framer(s) to map/demap ATM cells or packets into as many as four DS3/E3 digital lines with DS3-framed, E3-framed, or clear- channel data streams on per-port basis. APPLICATIONS Access Concentrators Multiservice Access Platform (MSAP) ...
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... Generation, Detection, and Analysis DETAILED DESCRIPTION The DS3161 (single), DS3162 (dual), DS3163 (triple), and DS3164 (quad) PHYs perform all the functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3 (34.368Mbps) framed, or 52Mbps clear-channel data streams. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival ...
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BLOCK DIAGRAM 2 APPLICATIONS 3 FEATURE DETAILS 3 ........................................................................................................................................ 16 LOBAL EATURES 3.2 R DS3/E3 F ECEIVE RAMER 3.3 R PLCP F ECEIVE RAMER 3 ECEIVE ELL ROCESSOR 3 ECEIVE ACKET ...
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Microprocessor Interface Functional Timing ........................................................................................ 85 8.3.7 JTAG Functional Timing....................................................................................................................... 90 9 INITIALIZATION AND CONFIGURATION 9 ONITORING AND EBUGGING 9.1.1 Cell/Packet FIFO.................................................................................................................................. 93 9.1.2 Cell Processor...................................................................................................................................... 93 9.1.3 Packet Processor ................................................................................................................................. 93 10 FUNCTIONAL DESCRIPTION 10.1 P ...
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System Loopback............................................................................................................................... 145 10.8 DS3/E3 PLCP F .............................................................................................................................. 146 RAMER 10.8.1 General Description ........................................................................................................................... 146 10.8.2 Features ............................................................................................................................................. 146 10.8.3 Transmit PLCP Frame Processor ...................................................................................................... 147 10.8.4 Receive PLCP Frame Processor ....................................................................................................... 147 10.8.5 Transmit DS3 PLCP Frame Processor ...
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Features ............................................................................................................................................. 190 10.15.3 Configuration and Monitoring............................................................................................................. 190 10.15.4 Receive Pattern Detection ................................................................................................................. 191 10.15.5 Transmit Pattern Generation.............................................................................................................. 193 11 OVERALL REGISTER MAP 12 REGISTER MAPS AND DESCRIPTIONS 12 .................................................................................................................................. 197 EGISTERS IT APS 12.1.1 Global ...
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ELL ACKET ROCESSOR 12.14.1 Transmit Cell Processor Register Map .............................................................................................. 325 12.14.2 Receive Cell Processor...................................................................................................................... 333 12.14.3 Transmit Packet Processor Register Map ......................................................................................... 345 12.14.4 Receive Packet Processor Register Map .......................................................................................... 350 13 JTAG INFORMATION 13.1 ...
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Figure 1-1. DS316x Functional Block Diagram ........................................................................................................... 2 Figure 2-1. Four-Port Unchannelized ATM over DS3/E3/CC52 Line Card ............................................................... 14 Figure 2-2. Four-Port Unchannelized HDLC over DS3/E3/CC52 Line Card ............................................................. 15 Figure 6-1. DS3/E3 ATM/Packet Mode ..................................................................................................................... 25 Figure 6-2. DS3/E3 ...
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Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing........................................... 85 Figure 8-40. 16-Bit Mode Write.................................................................................................................................. 86 Figure 8-41. 16-Bit Mode Read ................................................................................................................................. 86 Figure 8-42. 8-Bit Mode Write.................................................................................................................................... 87 Figure 8-43. 8-Bit Mode Read ................................................................................................................................... 87 Figure 8-44. ...
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... Figure 13-2. JTAG TAP Controller State Machine .................................................................................................. 362 Figure 13-3. JTAG Functional Timing...................................................................................................................... 365 Figure 14-1. DS3164 Pin Assignments—400-Lead BGA ........................................................................................ 366 Figure 14-2. DS3163 Pin Assignments—400-Lead BGA ........................................................................................ 367 Figure 14-3. DS3162 Pin Assignments—400-Lead BGA ........................................................................................ 368 Figure 14-4 DS3161 Pin Assignments—400-Lead BGA......................................................................................... 369 Figure 18-1 ...
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Table 4-1. Standards Compliance ............................................................................................................................. 22 Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers................................................................................ 25 Table 6-2. DS3/E3 ATM/Packet—OHM Mode Configuration Registers.................................................................... 26 Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers ................................... 27 Table 6-4. DS3/E3 External Fractional (XFRAC) ...
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Table 11-1. Global and Test Register Address Map ............................................................................................... 195 Table 11-2. Per Port Register Address Map............................................................................................................ 196 Table 12-1. Global Register Bit Map........................................................................................................................ 197 Table 12-2. System Interface Bit Map ..................................................................................................................... 198 Table 12-3. Port Register Bit Map ........................................................................................................................... ...
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Table 17-2. DC Electrical Characteristics................................................................................................................ 372 Table 17-3. Output Pin Drive ................................................................................................................................... 373 Table 18-1. Fractional Port Timing .......................................................................................................................... 376 Table 18-2. Line interface Timing ............................................................................................................................ 376 Table 18-3. Miscellaneous Pin Timing..................................................................................................................... 377 Table 18-4. Overhead Port Timing .......................................................................................................................... 377 ...
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APPLICATIONS Access Concentrators Multi-Service Access Platforms ATM and Frame Relay Equipment Routers and Switches SONET/SDH ADM SONET/SDH Muxes PBXs Digital Cross Connect PDH Multiplexer/Demultiplexer Test Equipment Integrated Access Device (IAD) Figure 2-1 and Figure 2-2 show applications for the ...
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Figure 2-2. Four-Port Unchannelized HDLC over DS3/E3/CC52 Line Card Typical Packet Line Card DS315x #1 DS3154 #1 4- Chan 4- Chan x DS3/E3 DS3/E3 DS3/E DS3/E3 Line Line LIU LIU DS318x DS3154 #3 DS315x #3 4- Chan 4- Chan x ...
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... FEATURE DETAILS The following sections describe the features provided by the DS3161 (single), DS3162 (dual), DS3163 (triple), and DS3164 (quad) PHYs. • Each port independently configurable • Universal PHYs map ATM cells and/or HDLC packets into DS3 or E3 data streams • UTOPIA L2/L3 or POS-PHY L2/L3 OR SPI-3 interface with 8-, 16-, or 32-bit bus • ...
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Clear-channel HDLC at line rates Mbps • In UTOPIA bus mode, ports are independently configurable for any ATM protocol • In POS-PHY bus mode, ports are independently configurable for any ATM or HDLC protocol • Programmable ...
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Performance monitoring counters for forwarded cells, corrected cells, uncorrectable cells, header pattern match/no-match cells, and filtered idle/unassigned/invalid cells • Octet alignment option for externally defined frame formats 3.5 Receive Packet Processor Features • Packet de-scrambling using the self-synchronizing scrambler ...
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Single-bit and multiple-bit header error insertion for diagnostics • Controls include enables/disables/settings for: cell processing, HEC insertion, coset polynomial addition, cell scrambling, fill cell type, error insertion type/rate/count, HEC bit corruption • Counter for number of cells read from ...
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HDLC Overhead Controller Features • Each port has a dedicated HDLC controller for DS3/E3 framer or PLCP link management • 256-byte receive and transmit FIFOs • Handles all of the normal Layer 2 tasks including zero stuffing/de-stuffing, FCS generation/checking, ...
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Two programmable I/O pins per port 3.21 Subrate Features (Fractional DS3/E3) • Independent per port built-in support for subrate DS3 or E3 • Independent subrate operation for both RX and TX data paths • Subrate operation for each channel ...
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STANDARDS COMPLIANCE Table 4-1. Standards Compliance SPECIFICATION ANSI T1.102-1993 Digital Hierarchy – Electrical Interfaces T1.107-1995 Digital Hierarchy – Formats Specification T1.231-1997 Digital Hierarchy – Layer 1 In-Service Digital Transmission Performance Monitoring T1.404-1994 Network-to-Customer Installation – DS3 Metallic Interface Specification ...
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SPECIFICATION I.432 B-ISDN User-Network Interface – Physical Layer Specification, March, 1993 Error Performance Measuring Equipment Operating at the Primary Rate and Above, O.151 October, 1992 Q.921 ISDN User-Network Interface – Data Link Layer Specification, March 1993 OIF System Packet Interface ...
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ACRONYMS AND GLOSSARY Definition of the terms used in this datasheet: Acronyms • ATM – Asynchronous Transfer Mode • CC52 – Clear-Channel 52 Mbps (STS-1 Clock Rate) • CLAD – Clock Rate Adapter • CLR – Clear-Channel Mode • ...
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MAJOR OPERATIONAL MODES The major operational modes are determined by the FM[5:0] framer mode bitsand a few other control bits. Unused features are powered down and the data paths are held in reset. The configuration registers of the unused ...
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DS3/E3 ATM/Packet—OHM Mode DS3/E3 ATM/Packet—OHM Mode is a normal mode of operation for the DS316x device, which maps/de-maps ATM cells or packet data into a DS3 or E3 data stream, supporting externally defined framing protocols. Major functional blocks for ...
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DS3/E3 Internal Fractional (Subrate) ATM/Packet Mode DS3/E3 Internal Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the fractional overhead internally controlled. Major functional blocks for the DS3/E3 Internal Fractional Mode are shown ...
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DS3/E3 External Fractional (Subrate) ATM/Packet Mode DS3/E3 External Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the fractional overhead externally controlled. Major functional blocks for the DS3/E3 Internal Fractional Mode are shown ...
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DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Mode DS3/E3 Flexible External Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the fractional overhead and payload externally multiplexed. Major functional blocks for the DS3/E3 ...
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DS3/E3 G.751 PLCP ATM Mode DS3/E3 G.751 PLCP ATM mode is a normal mode of operation for the DS316x device, which maps/de-maps ATM cells into/from the DS3/E3 PLCP data stream. Major functional blocks for the DS3/E3 ATM/Packet mode are ...
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DS3/E3 G.751 PLCP ATM—OHM Mode DS3/E3 G.751 PLCP ATM—OHM mode is a normal mode of operation for the DS316x device, which maps/de- maps ATM cells into/from the DS3/E3 PLCP data stream, supporting externally defined framing modes. Major functional blocks ...
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Figure 6-7. DS3/E3 G.751 PLCP ATM—OHM Mode TOHMIn TUA1 TDATn TOHMOn TLCLKn RLCLKn RDATn ROHMIn Clock Rate Adapter DS3/E3 Transmit TX PLCP Formatter TRAIL FEAC HDLC TRACE DS3/E3 Receive Framer UA1 IEEE 1149.1 GEN JTAG Test Access Port Tx Cell ...
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Clear-Channel ATM/Packet Mode The Clear-Channel ATM/Packet Mode maps/de-maps ATM cells or HDLC packets into/from a serial datastream, bypassing the DS3/E3 formatter/framer. Major functional blocks for the Clear-Channel ATM/Packet Mode are shown in Figure 6-8. Mapping configuration is programmable on ...
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Clear-Channel ATM/Packet—OHM Mode The Clear-Channel ATM/Packet—OHM Mode maps/de-maps ATM cells or HDLC packets into/from a serial datastream, bypassing the DS3/E3 formatter/framer, supporting externally defined framing modes. Major functional blocks for the Clear-Channel ATM/Packet—OHM Mode are shown in programmable on ...
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Clear-Channel Octet Aligned ATM/Packet—OHM Mode The Clear-Channel Octet Aligned ATM/Packet—OHM Mode maps/de-maps ATM cells or HDLC packets into/from a serial datastream, bypassing the DS3/E3 formatter/framer, supporting arbitrary framing modes. Major functional blocks for the Clear-Channel Octet Aligned ATM/Packet—OHM Mode ...
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MAJOR LINE INTERFACE OPERATING MODES The line interface modes provide the following function: 1. Selection of the line coding type: i.e., B3ZS/HDB3/AMI or UNI. 7.1 HDB3/B3ZS/AMI Line Interface Mode The Line Interface Mode outputs/inputs a digital representation of AMI ...
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UNI Line Interface Mode This mode is valid for all framing modes, providing a digital NRZ input/output on RDATn and TDATn and clocked by RLCLKn and TLCLKn. The B3ZS/HDB3 decoder/encoder block is disabled except for the BPV counter, which ...
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UNI Line Interface—OHM Mode The line interface is forced into UNI mode when the framer is in any OHM mode; therefore, the LM bits are Don’t Cares. This mode is the same as the UNI Line Interface Mode except ...
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PIN DESCRIPTIONS Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for isolation of interconnect failures. 8.1 Short Pin Descriptions Table 8-1. DS3164 Short Pin Descriptions n = 1,2,3,4 (port ...
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NAME TYPE UTOPIA L2/3 OR POS-PHY L2/3 OR SPI-3 SYSTEM INTERFACE TSCLK I TADR[4] TADR[3] TADR[2] I TADR[1] TADR[0] TDATA[31] TDATA[30] TDATA[29] TDATA[28] TDATA[27] TDATA[26] TDATA[25] TDATA[24] TDATA[23] TDATA[22] TDATA[21] TDATA[20] TDATA[19] TDATA[18] TDATA[17] TDATA[16] I TDATA[15] TDATA[14] TDATA[13] TDATA[12] ...
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NAME TYPE RADR[4] RADR[3] RADR[2] I RADR[1] RADR[0] RDATA[31] RDATA[30] RDATA[29] RDATA[28] RDATA[27] RDATA[26] RDATA[25] RDATA[24] RDATA[23] RDATA[22] RDATA[21] RDATA[20] RDATA[19] RDATA[18] RDATA[17] RDATA[16] Oz RDATA[15] RDATA[14] RDATA[13] RDATA[12] RDATA[11] RDATA[10] RDATA[9] RDATA[8] RDATA[7] RDATA[6] RDATA[5] RDATA[4] RDATA[3] RDATA[2] RDATA[1] ...
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NAME TYPE D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] I/O Data [15:0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[10] A[9] A[8] A[7] A[6] I Address [10:1] A[5] A[4] A[3] A[2] A[1] A[0] / BSWAP Address [0] / ...
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NAME TYPE CLKA I Clock A CLKB I/O Clock B CLKC I/O Clock C VSS PWR Ground, 0V Potential VDD PWR Digital 3.3V AVDDC PWR Analog 3.3V for CLAD N.C. N.C. No Connection. Unused. FUNCTION CLAD POWER NO CONNECTS PIN ...
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Detailed Pin Descriptions Table 8-2. Detailed Pin Descriptions n = 1,2,3,4 (port number); Ipu (input with pullup); Oz (output tri-stateable, needs an external pullup or pulldown resistor to keep from floating); Oa (analog output); Ia (analog input); I/O (bidirectional ...
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PIN TYPE Transmit Negative AMI / Line OH Mask TNEGn: When the port line is configured for B3ZS, HDB3 or AMI mode and the framer is not configured for one of the “-OHM” modes (see this pin indicates that a ...
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PIN TYPE the positive clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The signal is typically referenced to the RLCLKn line clock ...
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PIN TYPE transitions high to low. This signal can be inverted. Receive Overhead ROHn: When the port framer is configured for one of the DS3 or E3 framing modes, this signal outputs the value of the receive overhead bits. The ...
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PIN TYPE Transmit Start Of Frame Input / OH Mask Input See Table 10-18. TSOFIn: When the port framer is configured for any of the DS3 or E3 non “-OHM” framed modes, this signal can be used to align the ...
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PIN TYPE Transmit Payload Data Enable Input / PLCP Overhead Enable / Fractional OH Enable Input / See Table 10-20. TPDENIn: When the port is configured for the Flexible fractional mode, this pin is used to enable payload data from ...
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PIN TYPE TDENn / See Table 10-21. TPOHSOFn / TSOFOn: When the port framer is configured for the External Fractional or Flexible TFOHENOn Fractional modes and the port pins are enabled and the TSOFOn pin function is selected, this signal ...
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PIN TYPE Transmit Payload Data See Table 10-24. TPDATn: When the port framer is enabled for the Flexible fractional mode and the port pins are enabled, this signal is the payload bits from the cell/packet processor. The data is valid ...
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PIN TYPE bits. The RPOHSOFn signal marks the start of the framing bit sequence. This signal is updated at the same time as the RPOHCLKn signal transitions high to low. This signal can be inverted.. Receive Clock Output / Gapped ...
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PIN TYPE Receive Framer Start Of Frame /Data Enable / PLCP Overhead Start Of Frame See Table 10-28. RSOFOn: When the port framer is configured for External Fractional or Flexible Fractional mode and the RSOFOn pin function is enabled, or ...
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PIN TYPE In 8-bit mode, TDATA[7] is the MSB, TDATA[0] is the LSB, and TDATA[31:8] are not used and ignored. Transmit Parity TPRTY: This signal indicates the parity on the data bus when parity checking is TPRTY I enabled. This ...
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PIN TYPE updated on the rising edge of TSCLK. In UTOPIA L3 mode this signal is low. In POS-PHY L2 mode, this signal is driven when one of the ports is selected for data transfer, and tri-state when TEN is ...
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PIN TYPE Receive Data [31:0] (tri-state) This signal is tri-state when global reset is applied. RDATA[31:0]: This 32-bit data bus is used to transfer cell/packet data to the ATM/Link layer device. This bus is updated on the rising edge of ...
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PIN TYPE In UTOPIA L2 or UTOPIA L3 modes, RPXA goes high when the polled port has more than a programmable number of ATM cells ready for transfer ("almost empty" level). RPXA goes low when the polled port does not ...
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PIN TYPE Receive packet data Valid(tri-state) This signal is tri-state when global reset is applied. RVAL: In POS-PHY L2 or POS-PHY L3 modes, this signal is used to indicate the validity of a receive data transfer. When RVAL is high, ...
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PIN TYPE outputs during register reads. The upper 8 bits are not used and never driven in 8-bit bus mode. Weak pullup resistors or bus holders should be used for each pin. Address bus (minus LSB) A[10:1] I A[10:1]: identifies ...
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PIN TYPE General-Purpose I/O 2 GPIO2 I/O GPIO2: This signal is configured general-purpose I/O pin, or the 8KREFO output signal alarm output signal for port 1. General-Purpose I/O 3 GPIO3 I/O GPIO3: This signal is ...
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PIN TYPE JTAG Reset (active low with pullup) JTRST: This input forces the JTAG controller logic into the reset state and forces the JTRST JTDO pin into high impedance when low. This pin should be low while power is Ipu ...
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Pin Functional Timing 8.3.1 Line I/O 8.3.1.1 B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing There is no suggested time alignment between the TX LINE signals and the TLCLKn clock signal. The TX DATA signal is not a readily available signal, ...
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B3ZS/HDB3/AMI Mode Receive Pin Functional Timing There is no suggested time alignment between the RX LINE signals and the RLCLKn clock signal. The RX DATA signal is not an always readily available signal meant to represent the ...
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TOHMOn is high. In the “- OHM Octet” framing modes, the first payload bit after the TOHMOn signal goes low is the MSB (Bit payload Octet. The TDATn and TOHMOn signals change a small delay ...
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Figure 8-7. RX Line I/O OHM UNI Functional Timing Diagram RLCLK RDAT ROHM RLVC INC BPV COUNTER TWICE Figure 8-8. RX Line I/O UNI Octet Aligned OHM Functional Timing Diagram RLCLK EXT OH BIT LOCATIONS RDAT Octet ...
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Figure 8-11 shows the relationship between the E3 G.832 receive overhead port pins. Figure 8-11. E3 G.832 Framing Receive Overhead Port Timing ROHCLK ROHSOF FA1 FA1 ROH ...
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Figure 8-15 shows the relationship between the DS3 PLCP receive overhead port pins. Figure 8-15. DS3 PLCP Receive Overhead Port Timing TOHCLK TOHSOF TOHEN FA1 FA1 TOH ...
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Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing The fractional overhead pins provide the ability to insert bits in the DS3/E3 payload that are not used for cells or packets. The source of fractional overhead bits is ...
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Figure 8-22 shows the timing with the internal fractional transmit port pins Figure 8-22. Internal (IFRAC) Receive Fractional Timing RCLKI or RCLKO RGCLK RFOHENO RSER FOH FOH 8.3.4 Flexible Fractional (FFRAC) DS3/E3 Overhead ...
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Figure 8-24 shows the timing with the flexible fractional receive port pins Figure 8-24. Receive Flexible Fractional (FFRAC) Timing RCLKI or RCLKO RSOFO RDEN RSER FP4 FP5 FP6 FO1 FO2 RPDENI RSER ...
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UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing 8.3.5.1 UTOPIA Level 2 Functional Timing Figure 8-25 shows a multi-device transmit interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device places address ‘00h’ on the address bus ...
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Figure 8-26 shows a multi-device transmit interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device places address ‘00h’ on the address bus (which is mapped to Port 1). PHY device '1' (Port 1) indicates ...
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Figure 8-27 shows a multi-device transmit interface multiple cell transfer to different PHY devices. On clock edge 2, the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it can ...
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Figure 8-28 shows a multi-device receive interface multiple cell transfer from different PHY devices. On clock edge 2, the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it has ...
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Figure 8-29 shows a multi-device receive interface unexpected multiple cell transfer. Prior to clock edge 1, the cell transfer was started. On clock edge 4, since no other PHY device has a cell ready for transfer, the ATM device assumes ...
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UTOPIA Level 3 Functional Timing Figure 8-30 shows a multi-port transmit interface multiple cell transfer to different PHY devices. PHY port '1', ‘3’, ‘4’ indicate to the ATM device that they can accept cell data by asserting the TDXA[n]. ...
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Figure 8-31 shows a multi-port transmit interface multiple cell transfer to different PHY devices. On clock edge 1, the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it can ...
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Figure 8-32 shows a multi-port receive interface multiple cell transfer from different PHY ports. On clock edge 3, PHY port 'N' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock ...
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Figure 8-33 shows a multi-port receive interface multiple cell transfer from different PHY ports. On clock edge 1, the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it has ...
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POS-PHY Level 2 Functional Timing Figure 8-34 shows a multi-device transmit interface in byte transfer mode multiple packet transfer to different PHY ports. Prior to clock edge 1, the POS device started a packet transfer to PHY port '1'. ...
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Figure 8-35 shows a multi-device receive interface in byte transfer mode multiple packet transfer from different PHY ports/devices. Prior to clock edge 1, a packet data transfer was initiated from PHY port '1', and PHY ports '2', '3', and '4' ...
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Figure 8-36 shows a multi-device transmit interface in packet transfer mode multiple packet transfer to different PHY ports. On clock edge 2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS ...
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Figure 8-37 shows a multi-device receive interface in packet transfer mode multiple packet transfer. On clock edge 2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS device that it has ...
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POS-PHY Level 3 Functional Timing Figure 8-38 shows a multi-port transmit interface multiple packet transfer to different PHY ports. On clock edge 1, PHY port 'N' indicates to the POS device that it can accept a block of packet ...
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Figure 8-39 shows a multi-port receive interface multiple packet transfer from different ports. On clock edge 1, the POS device indicates to PHY port 'N' that it is ready to accept a block of packet data by asserting REN. On ...
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Figure 8-40. 16-Bit Mode Write A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 Figure 8-41. 16-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 ...
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Figure 8-42. 8-Bit Mode Write A[0]/BSWAP A[10:1] 0x2B0 D[7:0] 0x34 RDY Z Note: Address 0x2B0 = 0x34 0x2B1 = 012 Figure 8-43. 8-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[7:0] 0x34 RDY Z Note: Address ...
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Figure 8-44. 16-Bit Mode without Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 0x2B2 = 0x5678 Figure 8-45. 16-Bit Mode with Byte Swap A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x3412 ...
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Figure 8-46. Clear Status Latched Register on Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 8-47. Clear Status Latched Register on Write A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Figure 8-48 and Figure ...
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Figure 8-48. RDY Signal Functional Timing Writes A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Figure 8-49. RDY Signal Functional Timing Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z See also Figure 18-7 and Figure ...
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... Current device ID codes are: DS3161 rev 1.0: o DS3162 rev 1.0: o DS3163 rev 1.0: o DS3164 rev 1.0: o STEP 2: Initialize the Device. Before configuring for operation, make sure the device known condition with all registers set to their default value by initiating a Global Reset ...
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STEP 9: Configure the System Bus Configure for bus size and for interface type. See Optionally, set the System Interface Transmit Control Register, System Interface Receive Control Register #1 and #2 to fine tune for the specific application. (User may ...
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Considerations Select the HDLC Controller connection. The default setting connects it to the DS3/E3 Framers. PORT.CR1.HDSEL = 1 connects the HDLC Controller to the PLCP framers. In POS-PHY mode, to select cell processing rather than packet processing, set PORT.CR2.PMCPE = ...
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FUNCTIONAL DESCRIPTION 10.1 Processor Bus Interface 10.1.1 8/16-Bit Bus Widths The external processor bus can be sized for bits using the WIDTH pin. When in 8-bit mode (WIDTH=0), the address is composed of all the address ...
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... A valid port is a port that is available in a particular packaged part. For example, port four would not be valid in a DS3163 device. After reset, the global write method is not enabled. When the GWM bit is set, read data from the port registers is not valid and read data from the global and test registers is valid ...
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Figure 10-1. Interrupt Structure SRL bit SRIE bit SRL bit SRIE bit SRL bit SRIE bit BLOCK LATCHED STATUS and INTERRUPT ENABLE REGISTERS Figure 10-1 not only tells the user how to determine which event caused the interrupt, it also ...
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Clocks 10.2.1 Line Clock Modes The system loopback (SLB) function does not affect the line clocks in any way. 10.2.1.1 Loop Timing When loop timing is enabled (PORT.CR3.LOOPT), the transmit clock source is the same as the receive clock ...
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Sources of Clock Output Pin Signals The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks pins (TCLKIn), the receive clock input pins (RLCLKn), and the clock signals in the ...
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Figure 10-2. Internal TX Clock PORT.CR3. CLADC CLAD 0 TCLKI 1 RCLKO Table 10-3 identifies the source of the output signal TCLKOn based on certain variables and register bits. Table 10-3. Source Selection of TCLKOn (internal TX clock) Signal LOOPT ...
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Transmit Line Interface Pins Timing Source Selection (TPOSn/TDATn, TNEGn/TOHMOn) The transmit line interface signal pin group has the same functional timing clock source as the TLCLKn pin described in Table 10-2. Other clock pins can be used for the ...
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Table 10-6. Transmit Framer Pin Signal Timing Source Select LBM[2:0] 1 XXX 1 XXX 0 PLB (011) or DLB (100) or ALB(001) 0 DLB&LLB (110) 0 LLB (010) 0 not LLB, DLB or PLB (00X) 0 not PLB (011) 0 ...
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Clock Structures On Signal IO Pins The signals on the input pins (RFOHENIn, TOHMIn/TSOFIn, TFOHn/TSERn, TFOHENIn) can be used with any of the clock pins for setup/hold timing on clock input and output pins. There will be a flop ...
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OR of the RCLKOn and RDENn signals. When the output clock is disabled, the gapped output signal is high during ...
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Figure 10-4. Reset Sources RST pin NOTE: Assumes active high signals Table 10-8. Reset and Power-Down Sources Register bit states - F0: Forced to 0, F1: Forced Set Set Don’t care ...
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After a global reset, all of the control and status registers in all ports are set to their default values and all the other flops are reset to their reset values. The global register GL.CR1.RSTDP, and the port register PORT.CR1.RSTDP ...
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Figure 10-5. CLAD Block CLKA CLKB CLKC The clock rate adapter can also be disabled and all three clocks supplied externally using the CLKA, CLKB and CLKC pins as clock inputs. When the CLAD is disabled, the three reference clocks ...
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Table 10-9. CLAD IO Pin Decode GL.CR2. CLKA PIN CLAD[3: DS3 clock input 01 00 DS3 clock input 01 01 DS3 clock input 01 10 DS3 clock input 01 11 DS3 clock input clock input ...
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Table 10-10. Global 8kHz Reference Source Table GL.CR2. GL.CR2. Source G8KIS G8KRS[2:0] 0 None, the 8KHZ divider is disabled. 000 0 001 Derived from CLAD DS3 clock output or CLKA pin if CLAD is disabled. (Note: CLAD is disabled after ...
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The 8 kHz reference logic tree is shown below. Figure 10-6. 8KREF Logic G8KRS[1:0] FROM CLAD DS3 CLK E3 CLK STS-1 CLK GPIO4 RX PLCP 8KREF P8KRS[0] RX CLOCK TX CLOCK FRAME MODE 10.4.3 One-Second Reference Generation The one-second reference ...
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Table 10-12. GPIO Global Signals Pin Global signal GPIO2 8KREFO output GPIO4 8KREFI input GPIO6 TMEI input GPIO8 PMU input Table 10-13 describes the selection of mode for the GPIO Pins. Table 10-13. GPIO Pin Global Mode Select Bits n ...
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Performance Monitor Counter Update Details The performance monitor counters are designed to count at least one second of events before saturating to the maximum count. There is a status bit associated with some of the performance monitor counters that ...
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Figure 10-8. Transmit Error Insert Logic PORT.CR.MEIMS PORT.CR.TMEI GL.CR1.MEIMS GL.CR1.TMEI GPIO6 PIN (TMEI) 10.5 Per Port Resources 10.5.1 Loopbacks There are several loop back paths available. The following table lists the loopback modes available for analog loopback (ALB), line loopback ...
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Figure 10-9 highlights where each loopback mode is located and gives an overall view of the various loopback paths available. Figure 10-9. Loopback Modes TAIS TUA1 B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder Clock Rate Adapter 10.5.1.1 Terminal Loopback (TLB) Terminal ...
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Diagnostic Loopback (DLB) Diagnostic loopback is enabled by setting PORT.CR4.LBM[2:0] = 1XX. DLB and LLB are enabled at the same time when LBM[2:0] = 110, only DLB is enabled when LBM[2:0] = 10X or 111. The Diagnostic loopback sends ...
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The receive framer can detect both unframed all ones AIS and DS3 framed AIS patterns. When in DS3 framing modes, both framed DS3 AIS and unframed all ones can be detected framing modes E3 AIS, which is unframed ...
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Table 10-16 lists the LAIS decodes for various line AIS enable modes. Table 10-16. Line AIS Enable Modes LAIS[1:0] Frame Mode PORT.CR1 00 DS3 Clear Channel 01 Any 10 DS3 Clear Channel 11 Any ...
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Trail Trace There is a single Trail Trace controller for use in line maintenance protocols. The E3-G.832 and PLCP framers can use the trail trace controller and it is shared automatically since the E3-G.832 and PLCP framing can not ...
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Table 10-19. TSERn / TPOHn / TFOHn Input Pin Functions FM[5:0] TPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) X 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) 1 0XX110 (FFRAC) X 1XX0XX (CLR) X Table 10-20. ...
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Table 10-22. TCLKOn / TGCLKn / TPOHCLKn Output Pin Functions FM[5:0] TPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) 0 0XX00X (FRM) 1 0XX00X (FRM) 1 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) ...
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Table 10-25. RSERn / RPOHn Output Pin Functions FM[5:0] RPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) 0 0XX00X (FRM) 1 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX10X (PLCP) 0 0XX10X (PLCP) 1 0XX110 (FFRAC) X 1XX0XX (CLR) 0 1XX0XX ...
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Table 10-28. RSOFOn / RDENn / RPOHSOFn / RFOHENOn Output Pin Functions FM[5:0] RPFPE PORT.CR2 PORT.CR3 0XX00X (FRM) 0 0XX00X (FRM) 1 0XX00X (FRM) 1 0XX010 (IFRAC) 0 0XX010 (IFRAC) 1 0XX011 (XFRAC) X 0XX011 (XFRAC) X 0XX10X (PLCP) 0 ...
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ATM and packets and the packets become octet stuffed instead of bit stuffed. Refer to Table 10-30. Table 10-30. Framing Mode Select Bits FM[5:0] FM[5:0] DESCRIPTION 0 00 000 DS3 C-bit 0 00 001 DS3 ...
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Mapping Modes Cells and packets are mapped into various internally generated frame structures or mapped with no framing or mapped into an externally generated frame structure. When ATM cells are mapped into an internally generated frame structure they are ...
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Figure 10-12. DS3 PLCP Frame A1 A2 P11 P10 ...
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Figure 10-13. DS3 M23 (with C-bits used as payload) Frame 84 169 bits 11 bits ...
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Figure 10-15. E3 PLCP Frame ...
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Figure 10-17. E3 G.832 Frame FA1 FA2 10.5.12 Line Interface Modes The line interface modes can be selected semi-independently of the framing modes using the PORT.CR2.LM control bit. The major block enabled is the line ...
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UTOPIA/POS-PHY/SPI-3 System Interface 10.6.1 General Description The UTOPIA/POS-PHY system interface transports ATM cells or HDLC packets between the DS316x and an ATM or Link Layer device. In UTOPIA mode, the DS316x is connected to an ATM layer device and ...
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... Transfer th (n-1) Transfer th n Transfer Bit 0 Byte 2 Byte 1 Byte 6 Byte 5 • • • • • • Byte 4n-6 Byte 4n-7 Byte 4n-2 Byte 4n-3 DS3161/DS3162/DS3163/DS3164 st 1 Transfer nd 2 Transfer th (n-1) Transfer th n Transfer st 1 Transfer nd 2 Transfer th (n-1) Transfer th n Transfer ...
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... More than one PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte is transferred with the cells is programmable Transfer nd 2 Transfer th (n-1) Transfer th n Transfer DS3161/DS3162/DS3163/DS3164 ...
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The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[31:0]), receive parity (RPRTY), and receive start of cell (RSOX), as well ...
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POS-PHY Level 3 (or SPI-3), Transmit Side In POS-PHY Level 3 (or SPI-3), the Link layer device pushes packets across the system interface. The Link layer device polls the individual ports of the DS316x to determine which ports have ...
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RPRTY indicates the data bus parity. All signals are sampled and updated using RSCLK. The data bus is always driven. In POS-PHY Level 3 (or SPI-3) the Receive System Interface Bus Controller determines which port to transfer ...
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ATM Cell / HDLC Packet Processing 10.7.1 General Description The ATM cell / packet processing de-maps the ATM cells or HDLC packets from the receive data stream and maps ATM cells or HDLC packets into the transmit data stream. ...
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Programmable transmit cell synchronization – The transmit data line can be provisioned to be bit synchronous or octet-aligned. • PLCP or HEC based cell delineation – Cell delineation is determined from the PLCP frame during PLCP framing modes, and ...
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Receive Cell Processor is enabled. In POS-PHY mode, if the PORT.CR2.PMCPE bit is low, the Receive Packet Processor is enabled. If the PORT.CR2.PMCPE bit is high, the Receive Cell Processor is enabled. The bits in a byte are received ...
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Once all cell processing has been completed, in bit synchronous mode, the 8-bit parallel data stream is multiplexed into a serial data stream and passed on. In octet-aligned mode, the 8-bit parallel data stream is passed on. 10.7.5.2 Receive Cell ...
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Figure 10-24. Receive DSS Scrambler Synchronization State Diagram Steady 8 Cells Fail Verification Verification 32 Samples Loaded If cell processing is disabled, a cell boundary is arbitrarily chosen, and the data is divided into "cells" whose size is programmable. If ...
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DS3 clear-channel, STS-1 clear-channel, and E3 clear-channel modes. A “Delta” of six is used during all other modes including the DS3 clear-channel—OHM, STS-1 clear-channel—OHM, and E3 clear-channel—OHM modes. In bit synchronous mode, the ...
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If errored cell extraction is enabled, errored cells are discarded, and the errored cell count is incremented. If errored cell extraction is disabled, errored cells are passed on cell is received with ...
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Figure 10-28. Cell Format for 52-Byte Cell With 32-Bit Data Bus Bit 31 Header 1 Payload 1 Payload 5 • • • Payload 41 Payload 45 10.7.6 Packet Processor 10.7.6.1 Transmit Packet Processor The Transmit Packet Processor accepts data from ...
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If packet processing is disabled, stuffing is not performed. ...
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Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. In bit synchronous mode, bit destuffing is performed. Bit destuffing consists of discarding any '0' that directly follows five contiguous '1's. In octet-aligned ...
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In packet processing mode, all operations are byte based. The Transmit FIFO is considered empty when its memory does not contain any data. The Transmit FIFO is considered "almost empty" when its memory does not contain a packet end and ...
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System Loopback There is a system loopback available in the ATM/HDLC Mapper. The loopback can be performed on a per port basis. When a port is placed in system loopback, the data coming in from the System Interface is ...
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DS3/E3 PLCP Framer 10.8.1 General Description The PLCP Framer de-maps the ATM cells from the DS3/E3 PLCP data stream in the receive direction and maps ATM cells into the DS3/E3 PLCP data stream in the transmit direction. The receive ...
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Transmit PLCP Frame Processor The Transmit PLCP Frame Processor receives the ATM cells from the ATM/Packet Processor performs trailer generation, framing generation, error insertion, and overhead insertion. The bits in a byte are transmitted MSB first, LSB last. When ...
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Figure 10-30. DS3 PLCP Frame Format A1 A2 P11 P10 ...
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Transmit DS3 PLCP Frame Generation DS3 PLCP frame generator receives the incoming PLCP payload data stream, and overwrites all of the overhead byte locations. The first two bytes of each subframe are overwritten with the frame alignment bytes A1 ...
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Error insertion can be initiated by a register bit (PLCP.TEIR.TSEI) or initiated by the manual error insertion input (TMEI). Each error type is individually enabled by a register bit. The error insertion initiation type (register or input) is programmable. Once ...
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OOF condition is continuously absent for 1 ms. An LOF condition is terminated when an OOF condition is continuously absent for 1 ms. A Change Of Frame Alignment (COFA) is declared when the ...
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Figure 10-32. E3 PLCP Frame Format ...
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HDLC Overhead Processor interface). The F1 byte source is programmable (PLCP.TCR.TF1C[1:0]) (trail trace data link, HDLC, or register). The fourth byte of subframe 4 is overwritten with the B1 byte which is ...
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Receive E3 PLCP Frame Processor The Receive E3 PLCP Frame Processor performs E3 PLCP framing, byte destuffing, performance monitoring, and overhead extraction. The E3 PLCP frame format is shown in value of F6h and 28h respectively. P8 – P0 ...
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A word error increments the count once for each frame alignment word (A1, A2, and P#) that does not match its expected value ( per subframe). The detection of POI byte (P#) framing errors is programmable ...
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Fractional Payload Controller 10.9.1 General Description The Fractional Payload Controller allows the user to utilize a fraction of the DS3/E3 payload for ATM cell or HDLC packets. The unused DS3/E3 payload is considered fractional overhead and can be used ...
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Transmit Fractional Interface The Transmit Fractional Interface receives the payload data stream from the ATM/Packet Processor and inserts a fractional overhead stream. The incoming fractional overhead stream consists of fractional overhead (TFOHn), input fractional overhead enable (TFOHENIn), and output ...
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Figure 10-35. Data Group Format Data Group (g bits) Section A (a bits) Figure 10-36. Frame Format Frame (f bits) Data Group Data Group Data Group Section B (g-a bits) • • • Data Group Data Group Data Group ...
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DS3/E3 Framer / Formatter 10.10.1 General Description The Receive DS3/E3 Framer receives a unipolar DS3/E3 signal, determines frame alignment and extracts the DS3/E3 overhead in the receive direction. The Transmit DS3/E3 Formatter receives a DS3/E3 payload, generates framing, inserts ...
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Detects alarms and errors – Detects DS3 alarm conditions (SEF, OOMF, OOF, LOF, COFA, AIS, AIC, RDI, and Idle) and errors (framing, parity, and FEBE alarm conditions (OOF, LOF, COFA, AIS, and RDI/RAI) and errors (framing, parity, ...
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M framer is an off-line framer that only updates the data path frame counters when either an out of frame (OOF out of multiframe (OOMF) condition is present. The use of an off-line framer ...
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Figure 10-39. DS3 Subframe Framer State Diagram All 4 bit positions failed Verify 2 F-bits loaded The multiframe framer checks for a multiframe boundary. When the multiframe framer identifies a multiframe boundary, it updates the data path frame counters if ...
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Figure 10-40. DS3 Multiframe Framer State Diagram Verify If multiframe alignment OOF is disabled, an Out Of Frame (OOF) condition is declared when three or more out of the last sixteen consecutive subframe alignment bits (F-bits) have been errored, or ...
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AIS condition when it has been active for a total DS3 frames. The AIS integration counter is active (increments count) when an AIS signal is present inactive (holds count) when ...
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C-bit DS3 Framer/Formatter 10.10.5.1 Transmit C-bit DS3 Frame Processor The C-bit DS3 frame format is shown in DS3 Frame. Table 10-32. C-Bit DS3 Frame Overhead Bit Definitions Bit Definition Remote Defect Indication 1 2 (RDI) P ...
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Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off). The P-bits (P and P ) are ...
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Transmit C-bit DS3 AIS/Idle Generation C-bit DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the data stream payload is forced to a 1100 pattern with two ones immediately following ...
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Table 10-33. M23 DS3 Frame Overhead Bit Definitions Bit Definition Remote Defect Indication 1 2 (RDI Parity Bits and M Multiframe Alignment Bits Subframe ...
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Each error type (framing or P-bit parity) has a separate enable. Continuous error insertion mode inserts errors at every opportunity. Single error insertion mode inserts an error at the next opportunity when requested. The framing multi-error insertion modes (SEF or ...
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G.751 E3 Framer/Formatter 10.10.7.1 Transmit G.751 E3 Frame Processor The G.751 E3 frame format is shown in bit used to indicate the presence of an alarm to the remote terminal equipment the National use bit reserved for ...
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Transmit G.751 E3 Overhead Insertion Overhead insertion can insert any (or all) of the E3 overhead bits into the E3 frame. The FAS, A bit, and N bit can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, ...
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OOF condition is first detected. A bit error increments the count once for each bit in the FAS that does not match its expected value ( per frame. A word error increments the count once for ...
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Figure 10-43. MA Byte Format MSB 1 RDI REI RDI - Remote Defect Indicator REI - Remote Error Indicator SL - Signal Label MI - Multi-frame Indicator TM - Timing Marker Table 10-35 shows the function of ...
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The payload type is sourced from a register. The three register bits are inserted in the third, ...
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Transmit G.832 E3 AIS Generation G.832 E3 AIS generation overwrites the data stream with AIS. If transmit AIS is enabled, the data stream (payload and E3 overhead) is forced to all ones. 10.10.8.6 Receive G.832 E3 Frame Processor The ...
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... MA byte) identify the phase of the multiframe (00, 01, 10, or 11). The Table STATUS 000 Match 001 Mismatch XXX Mismatch 000 Mismatch 001 Match XXX Match 000 Mismatch 001 Match XXX Match YYY Mismatch DS3161/DS3162/DS3163/DS3164 10-35), a mismatch indication is set. ...
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MA byte) contains the timing source indicator bit indicated by the multiframe indicator bits (first, second, third, or fourth bit respectively). The four timing source indicator bits are extracted from the multiframe, integrated, ...
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The bits in a byte are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB last. The bits in a byte in an incoming signal are numbered in the order they are received, ...
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Transmit HDLC Overhead Processor The Transmit HDLC Overhead Processor accepts data from the Transmit FIFO, performs bit reordering, FCS processing, stuffing, packet abort sequence insertion, and inter-frame padding. A byte is read from the Transmit FIFO with a packet ...
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When inter-frame fill is flags, the number of bits between the end flag and the start flag will be an integer number of bytes ...
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Trail Trace Controller 10.12.1 General Description Each port has a dedicated Trail Trace Buffer for E3-G.832 or DS3/E3 PLCP link management The Trail Trace Controller performs extraction and storage of the incoming G.832 or PLCP trail access point identifier ...
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Figure 10-45. Trail Trace Controller Block Diagram B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder Clock Rate Adapter 10.12.2 Features • Programmable trail trace ID – The trail trace ID controller can be programmed to handle a 16-byte trail trace identifier (trail ...
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... The trail trace identifier bytes are stored sequentially with the first byte (MAS equals 1 if trail trace alignment is enabled) being stored in the first byte of memory. If the exact same non-zero trail Bit 4 Bit 5 Bit 6 DT[4] DT[5] DT[6] DS3161/DS3162/DS3163/DS3164 Figure 10-46). The MAS bits are Bit 7 Bit 8 LSB DT[7] DT[8] ...
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An Idle condition is declared ...
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Figure 10-47. FEAC Controller Block Diagram B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder Clock Rate Adapter 10.13.2 Features • Programmable dual codeword output – The transmit side can be programmed to output a single codeword ten times, one codeword ten times ...
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Receive FEAC Processor The Receive FEAC Processor accepts an incoming data line and extracts all overhead and performs FEAC code extraction, and Idle detection. Figure 10-48. FEAC Codeword Format LSB FEAC ...
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Figure 10-49. Line Encoder/Decoder Block Diagram B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder Clock Rate Adapter 10.14.2 Features • Performs bipolar to unipolar encoding and decoding – Converts a unipolar signal into an AMI bipolar signal (POS data, and NEG data) ...
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Transmit Line Interface The Transmit Line Interface accepts a bipolar data stream from the B3ZS/HDB3 Encoder, performs error insertion, and transmits the bipolar data stream. Error insertion inserts BPV or EXZ errors into the bipolar signal. When a BPV ...
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Figure 10-50. B3ZS Signatures RLCLK (RX DATA) RPOS RNEG RLCLK (RX DATA) V RPOS RNEG Figure 10-51. HDB3 Signatures RLCLK (RX DATA) RPOS RNEG RLCLK (RX DATA) V RPOS RNEG BPV detection checks the bipolar signal for bipolar violation (BPV) ...
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BERT 10.15.1 General Description The BERT is a software-programmable test-pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random patterns with a generation polynomial of the form ...
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Table 10-36. Pseudo-Random Pattern Generation PATTERN TYPE PTF[4:0] (hex O.153 (511 type O.152 and O.153 08 (2047 type O.151 O.153 O.151 QRSS ...
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Receive PRBS Synchronization PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next ...
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Figure 10-54. Repetitive Pattern Synchronization State Diagram 1 bit error Verify Pattern Matches 10.15.4.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out ...
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... The register addresses of the global, test and all four ports are concatenated to cover the address range of 000 to 7FF. The address map requires 11 bits of address, ADR[10:0]. The upper address bit A[10] is decoded for the DS3164 and DS3163 devices. The upper address bit A[10 not used by the DS3162 and DS3161 devices and must be tied low at the pin. ...
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... The following table is a map of the registers for each port. The address offset is from the start of each port range of 000h, 200h, 400h and 600h DS3163, writes to registers in port 4 will be ignored and reads from port 4 registers will read back zero values. Similarly DS3161, writes to registers in port 2 will be ignored and reads from port 2 will read back zero values ...
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Table 11-2. Per Port Register Address Map Port 1 Port 2 040 to 1FF 240 to 3FF Address Description offset 040 - 05F Port common registers 060 – 07F BERT 080 – 08B Reserved 08C – 08F B3ZS/HDB3 transmit line ...
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REGISTER MAPS AND DESCRIPTIONS 12.1 Registers Bit Maps Note: In 8-bit mode, register bits[15:8] correspond to the upper byte, and register bits[7:0] correspond to the lower byte. For example, address 001h is the upper byte (bits [15:8]) and address ...
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Table 12-2. System Interface Bit Map Address Type Bit 7 Register 16-bit 8-bit 030 030 SI.TCR RW 031 032 032 SI.TSRL RL 033 034 034 SI.TSRIE RW 035 036 036 UNUSED 037 038 038 SI.RCR1 RW 039 03A 03A SI.RCR2 ...
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Address Type Bit 7 Register 16-bit 8-bit J56 J56 PORT.SRIE RW J57 J58- J58- UNUSED J5E J5F Table 12-4. BERT Register Bit Map Address Type Bit 7 Register 16-bit 8-bit J60 J60 BERT.CR RW J61 J62 J62 BERT.PCR RW J63 ...
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Table 12-5. Line Register Bit Map Address Type Bit 7 Register 16-bit 8-bit J8C J8C LINE.TCR RW J8D J8E UNUSED J8E J8F J90 J90 LINE.RCR RW J91 J92 J92 UNUSED J93 J94 J94 LINE.RSR R J95 J96 J96 LINE.RSRL RL ...