DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 137

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
Once all cell processing has been completed, in bit synchronous mode, the 8-bit parallel data stream is multiplexed
into a serial data stream and passed on. In octet-aligned mode, the 8-bit parallel data stream is passed on.
10.7.5.2 Receive Cell Processor
The Receive Cell Processor performs cell de-scrambling, cell delineation, cell filtering, header pattern comparison,
OCD detection, HEC error monitoring, HEC byte filtering, and bit reordering. The data coming in can be either a
serial data stream (bit synchronous mode) or an 8-bit parallel data stream (octet-aligned mode). The type of data
stream received affects cell de-scrambling and cell delineation, however, it does not affect OCD detection, HEC
error monitoring, cell filtering, header pattern comparison, HEC byte filtering, or bit reordering. Cell processing can
be disabled (clear-channel enable). Disabling cell processing disables cell delineation, OCD detection, cell filtering,
header pattern comparison, HEC error monitoring, and HEC byte filtering. Only cell de-scrambling and bit
reordering are not disabled.
Cell de-scrambling can descramble the 48-byte cell payload, descramble the entire cell data stream, or descramble
a data stream scrambled by a Distributed Sample Scrambler (DSS). If the payload or the entire data stream is
43
descrambled, a self-synchronous scrambler with a generation polynomial of x
+ 1 is used for de-scrambling.
Payload de-scrambling, descrambles the 48-byte payload, and does not descramble the four header bytes or the
31
HEC
byte.
For a DSS scrambled data stream, a distributed sample scrambler with a generation polynomial of x
+
28
x
+ 1 is used for de-scrambling. The receive DSS scrambler is synchronized to the transmit DSS scrambler by
DSS scrambler synchronization. DSS de-scrambling can only be performed in bit synchronous mode. Cell de-
scrambling is programmable (payload, entire data stream, or DSS). In bit synchronous mode, de-scrambling is
performed one bit at a time, and the serial data stream is demultiplexed in to an 8-bit data stream before being
passed on. In octet-aligned mode, de-scrambling is performed 8-bits at a time, and only payload or entire data
stream de-scrambling can be performed. When cell processing is disabled, the entire data stream will be
descrambled if de-scrambling is enabled.
DSS Scrambler Synchronization synchronizes the receive DSS scrambler with the transmit DSS scrambler used to
scramble the incoming data stream. The DSS Scrambler Synchronization state machine has three states:
"Acquisition", "Verification", and "Steady State". The "Acquisition" state adds the transmit DSS scrambler samples
from 16 incoming cells into the receive DSS scrambler (32 samples total). The samples are derived from the two
MSBs (HEC[1:2]) of the incoming HEC byte. Each time the samples in a cell are loaded into the receive DSS
scrambler, the confidence counter is incremented. When the confidence counter reaches 16, DSS scrambler
synchronization transitions to the “Verification” state. The "Verification" state verifies the samples in the incoming
cells by comparing the samples from the cell with the corresponding receive DSS scrambler bits. Each time both
samples from a cell match the corresponding receive DSS scrambler bits, the confidence counter is incremented.
Each time one of the samples from a cell does not match the corresponding receive DSS scrambler bit, the
confidence counter is decremented if the confidence counter reaches 24, DSS scrambler synchronization
transitions to the “Steady State” state. If the confidence counter reaches 8, DSS scrambler synchronization
transitions to the “Acquisition” state. The "Steady State" state continues to verify the samples in the incoming cells.
Each time both samples from a cell match the corresponding receive DSS scrambler bits, the confidence counter is
incremented (maximum count = 24). Each time one of the samples from a cell does not match the corresponding
receive DSS scrambler bit, the confidence counter is decremented. If the confidence counter reaches 16, DSS
scrambler synchronization transitions to the “Acquisition” state. The DSS scrambler synchronization state diagram
is shown in
Figure
10-24. DSS scrambler synchronization starts in the “Acquisition” state. Note: All ATM cells are
discarded during the “Acquisition” and “Verification” states.