DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 184

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
trace identifier is received five consecutive times and it is different from the receive trail trace identifier, a receive
trail trace identifier update is performed, and the receive trail trace identifier change indication is set.
An Idle condition is declared when an all zeros trail trace identifier is received five consecutive times. An Idle
condition is terminated when a non-zero trail trace identifier is received five consecutive times or a TIU condition is
declared. A TIU condition is declared if eight consecutive trail trace identifiers are received that do not match either
the receive trail trace identifier or the previously stored current trail trace identifier. The TIU condition is terminated
when a non-zero trail trace identifier is received five consecutive times or an Idle condition is declared.
Expected trail trace comparison compares the received and expected trail trace identifiers. The comparison is a 7-
bit comparison of the seven least significant bits (DT[2:8] (see
Figure
10-46) of each trail trace identifier byte (The
multiframe alignment signal is ignored). If the received and expected trail trace identifiers do not match, a trail trace
identifier mismatch (TIM) condition is declared. If they do match the TIM condition is terminated. The 16-byte
expected trail trace identifier is programmable. Expected trail trace comparison is programmable (on or off). If
multiframe alignment is disabled, expected trail trace comparison is disabled. Immediately after a reset, the receive
trail trace identifier is invalid. All comparisons between the receive trail trace identifier and expected trail trace
identifier will match (a TIM condition cannot occur) until after the first receive trail trace identifier update occurs.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive Data Storage with the MSB in
RTD[7] and the LSB in RTD[0] of the receive trace ID data RTD[7:0]. If bit reordering is enabled, the incoming 8-bit
data stream DT[1:8] is output to the Receive Data Storage with the MSB in RTD[0] and the LSB in RTD[7] of the
receive trace ID data RTD[7:0]. DT[1] is the first bit received from the incoming data stream.
Once all of the trail trace processing has been completed, the 8-bit parallel data stream is passed on to the
Receive Data Storage.
10.12.9 Receive Data Storage
The Receive Data Storage block contains memory for 48 bytes of data, maintains data status information, and has
controller circuitry for reading and writing the memory. The Receive Data Storage controller functions include filling
the memory and maintaining the memory read and write pointers. The Receive Data Storage accepts data and
data status from the Receive Trace ID Processor, stores the data in memory, and maintains data status
information. The data is read from the Receive Data Storage via the microprocessor interface. The Receive Data
Storage contains the current trail trace identifier, the receive trail trace identifier, and the expected trail trace
identifier.
10.13 FEAC Controller
10.13.1 General Description
The FEAC Controller de-maps FEAC codewords from a DS3/E3 data stream in the receive direction and maps
FEAC codewords into a DS3/E3 data stream in the transmit direction. The transmit direction de-maps FEAC
codewords from a DS3/E3 data stream.
The receive direction performs FEAC processing, and stores the codewords in the FIFO using line timing. It
removes the codewords from the FIFO and outputs them to the microprocessor via the register interface.
The transmit direction inputs codewords from the microprocessor via the register interface and stores the
codewords. It removes the codewords and performs FEAC processing. See
Figure 10-47
for the location of
theFEAC Controller in the block diagram