DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 190

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.15 BERT
10.15.1 General Description
The BERT is a software-programmable test-pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random
patterns with a generation polynomial of the form x
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern. See
devices.
Figure 10-52. BERT Block Diagram
10.15.2 Features
•
•
•
•
•
10.15.3 Configuration and Monitoring
Set PORT.CR1.BENA = 1 to enable the BERT.
The following tables show how to configure the on-board BERT to send and receive common patterns. The BERT
must be enabled before the pattern is loaded for the pattern load operation to take affect.
Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (x
are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2
Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (the length n
= 1 to 32 and pattern = 0 to 2
24-bit error count and 32-bit bit count registers
Programmable bit error insertion – Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10
Pattern synchronization at a 10
random Bit Error Rate (BER) of 10
Adapter
Clock
Rate
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
n
is programmable (n = 1 to 7).
TUA1
TAIS
IEEE P1149.1
n
JTAG Test
Access Port
FEAC
- 1).
DS3 / E3
Transmit
Framer
DS3 / E3
Receive
Formatter
-3
Buffer
Trace
-3
Trail
.
BER – Pattern synchronization will be achieved even in the presence of a
HDLC
GEN
UA1
Figure 10-52
n
+ x
FRAC/
PLCP
y
TX
RX FRAC/
+ 1, where n and y can take on values from 1 to 32 and to
PLCP
for the location of the BERT Block within the DS316x
Processor
Processor
Processor
RX BERT
Processor
Tx Packet
TX BERT
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
n
- 1).
FIFO
Tx
FIFO
Rx
n
+ x
y
+ 1) and seed