DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 220

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3 UTOPIA/POS-PHY System Interface
12.3.1 Transmit System Interface
The transmit system interface block has three registers.
12.3.1.1 Register Map
Table 12-21. Transmit System Interface Register Map
12.3.1.2 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 13 to 8: Transmit Cell/Packet Available Deassertion Time (TXAD[5:0]) – These six bits indicate the
amount of data that can be transferred after the cell/packet available signal is deasserted. If more than the
indicated amount of data is transferred, a Transmit FIFO overflow may occur.
In UTOPIA mode, only TXAD[2:0] are valid, and they indicate the number of transfers into the FIFO before the
Transmit FIFO is full. For UTOPIA Level 2, a value of 00h enables the default mode, which is 5 (TDXA will
transition low on the edge that samples payload byte 43 in 8-bit mode, payload bytes 37 and 38 in 16-bit mode,
and payload bytes 25, 26, 27, and 28 in 32-bit mode). For UTOPIA Level 3, a value of 00h or 01h enables the
default mode. The default for UTOPIA Level 3 is for TDXA to transition low on the clock edge following the edge
that samples the start of a cell.
In POS-PHY mode, TXAD[5:0] indicate the number four byte data groups that can be written into the Transmit
FIFO before it is full (maximum value 56 or 38h). In POS-PHY Level 2, a value of 00h enables the default mode,
which is 1 (For an x-byte transfer, TDXA and TSPA will transition low on the edge that samples byte x-4 in 8-bit
mode, bytes x-5 and x-4 in 16-bit mode, and bytes x-7, x-6, x-5, and x-4 in 32-bit mode). In POS-PHY Level 3 (or
SPI-3) 8-bit, a value of 00h enables the default mode, which is 1 (For an x-byte transfer, TDXA and TSPA will
transition low on the edge that samples byte x-4). For POS-PHY Level 3 (or SPI-3) 16-bit and 32-bit mode, a value
of 00h or 01h enables the default mode, which is 2 (For an x-byte transfer, TDXA and TSPA will transition low on
the edge that samples bytes x-9 and x-8 in 16-bit mode and bytes x-11, x-10, x-9, and x-8 in 32-bit mode). Note: A
packet that is 4x+1, 4x+2, 4x+3, or 4x+4 (where x is an integer) bytes long consumes x+1 four byte data groups of
space in the FIFO. This includes 2-byte and 3-byte packets, which consume a four-byte data group of space in the
FIFO.
Bit 3: Transmit System Parity Polarity (TPARP) – When 0, the TPAR signal will maintain odd parity (for all 0''s,
TPAR is high). When 1, the TPAR signal will maintain even parity (for all 0''s, TPAR is low).
Address
030h
032h
034h
036h
15
--
--
0
7
0
SI.TSRIE
Register
SI.TSRL
SI.TCR
--
14
--
--
0
6
0
System Interface Transmit Control Register
System Interface Transmit Status Register Latched
System Interface Transmit Status Register Interrupt Enable
Unused
Register Description
SI.TCR
System Interface Transmit Control Register
030h
TXAD5
13
--
0
5
0
TXAD4
12
--
0
0
4
TPARP
TXAD3
11
0
3
0
TXAD2
TFLVI
10
0
2
0
TSBRE
TXAD1
9
0
1
0
THECT
TXAD0
8
0
0
0