DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 60

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GPIO3
GPIO2
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
JTCLK
JTMS
JTDO
TEST
JTDI
RST
PIN
HIZ
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ipu
Ipu
Oz
I
I
I
I
General-Purpose I/O 2
GPIO2: This signal is configured to be a general-purpose I/O pin, or the 8KREFO
output signal, or an alarm output signal for port 1.
General-Purpose I/O 3
GPIO3: This signal is configured to be a general-purpose I/O pin, or an alarm output
signal for port 2.
General-Purpose I/O 4
GPIO4: This signal is configured to be a general-purpose I/O pin, or the 8KREFI input
signal, or an alarm output signal for port 2. When configured for 8KREFI mode the
signal frequency should be 8,000 Hz ±500ppm and about 50% duty cycle.
General-Purpose I/O 5
GPIO5: This signal is configured to be a general-purpose I/O pin, or an alarm output
signal for port 3.
General-Purpose I/O 6
GPIO6: This signal is configured to be a general-purpose I/O pin, or the TMEI input
signal, or an alarm output signal for port 3. When configured for TMEI input, the signal
low time and high time must be greater than 500ns.
General-Purpose I/O 7
GPIO7: This signal is configured to be a general-purpose I/O pin, or an alarm output
signal for port 4.
General-Purpose I/O 8
GPIO8: This signal is configured to be a general-purpose I/O pin, or the PMU input
signal, or an alarm output signal for port 4. When configured for PMU input, the
signal low time and high time must be greater than 500 ns.
Test enable (active low)
TEST: This signal enables the internal scan test mode when low. For normal operation
tie high. This is an asynchronous input.
High-impedance test enable (active low)
HIZ: This signal puts all digital output and bi-directional pins in the high-impedance
state when it low and JTRST is low. For normal operation tie high. This is an
asynchronous input.
Reset (active low)
RST: This signal resets all the internal processor registers and logic when low. This
pin should be low while power is applied and set high after the power is stable. This
is an asynchronous input.
JTAG Clock
JTCLK: This clock input is typically a low frequency (less than 10MHz) 50% duty
cycle clock signal.
JTAG Mode Select (with pullup)
JTMS: This input signal is used to control the JTAG controller state machine and is
sampled on the rising edge of JTCLK.
JTAG Data Input (with pullup)
JTDI: This input signal is used to input data into the register that is enabled by the
JTAG controller state machine and is sampled on the rising edge of JTCLK.
JTAG Data Output
JTDO: This output signal is the output of an internal scan shift register enabled by the
JTAG controller state machine and is updated on the falling edge of JTCLK. The pin
is in the high-impedance mode when a register is not selected or when the JTRST
signal is high. The pin goes into and exits the high-impedance mode after the falling
edge of JTCLK
JTAG
FUNCTION