DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 84

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.5.4
Figure 8-38
PHY port 'N' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock
edge 3, the POS device selects PHY port 'N' by placing its address on TDATA and asserting TSX while TEN is de-
asserted. On clock edge 4, the POS device starts a packet transfer to PHY port 'N' by de-asserting TSX, asserting
TEN, placing the first byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of
the packet. On clock edge 5, the POS device de-asserts TSOX as it continues to place additional bytes of the
packet on TDATA and PHY port 'N' asserts TSPA. On clock edge 11, the POS device polls PHY port 'L'. On clock
edge 12, PHY port 'N' indicates that it cannot accept any more data transfers by de-asserting TSPA. On clock edge
13, PHY port 'L' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock
edge 14, the POS device de-asserts TEN to end the packet transfer process to PHY port 'N' and selects PHY port
'L' by placing its address on TDATA and asserting TSX while TEN is de-asserted. On clock edge 15, the POS
device starts a packet transfer to PHY port 'L' by asserting TEN, de-asserting TSX, placing the first byte of packet
data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock edge 16, the
POS device de-asserts TSOX as it continues to place additional bytes of the packet on TDATA and PHY port 'L'
asserts TSPA.
Figure 8-38. POS-PHY Level 3 Transmit Multiple Packet Transfer In-Band Addressing
Transfer
To PHY
TADR
TSOX
TERR
TEOP
TPXA
TDAT
TCLK
TSPA
TSX
TEN
POS-PHY Level 3 Functional Timing
shows a multi-port transmit interface multiple packet transfer to different PHY ports. On clock edge 1,
1
N
X
P
2
O
X
L
3
M
N
P
4
P1
N
L
5
P2
M
O
…
…
…
6
7
P38
M
P
8
P39
N
L
9
P40
N
M
O
10
P41
N
P
11
P42
L
O
12
P43
M
P
13
P44
N
L
14
M
O
L
15
P1
N
P
16
P2
O
L
17
L
P3
M
P
18
P4
N
L
19
P5
M
O
20
P6
N
P