DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 47

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ROHSOFn
ROHCLKn
TCLKIn
ROHn
PIN
DS3/E3 SERIAL DATA, PLCP AND FRACTIONAL DS3/E3 OVERHEAD INTERFACE
TYPE
O
O
O
I
transitions high to low.
This signal can be inverted.
Receive Overhead
ROHn: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal outputs the value of the receive overhead bits. The ROHSOFn signal
marks the start of the framing bit sequence. In T3 mode, the X-bits, P-bits, M-bits, F-
bits, and C-bits are output (Note: In M23 mode, the C-bits are extracted even though
they are marked as data at the payload interface). In G.751 E3 mode, all of the FAS,
RAI, and National Use bits are output. In G.832 E3 mode, all of the FA1, FA2, EM,
TR, MA, NR, and GC bytes are output.
This signal is updated at the same time as the ROHCLKn signal transitions high to
low.
This signal can be inverted.
Receive Overhead Clock
ROHCLKn: When the port framer is configured for one of the DS3 or E3 framing
modes, this clock is used for the receive overhead port signals ROHn and ROHSOFn.
The ROHSOFn and ROHn output signals are updated at the same time this clock
signal transitions from high to low. The external logic is expected to sample
ROHSOFn and ROHn signal on the rising edge of this clock signal. This clock is a low
frequency clock.
This signal can be inverted.
Receive Overhead Start Of Frame
ROHSOFn: When the port framer is configured for one of the DS3 or E3 framing
modes this signal is used to mark the start of a DS3 or E3 overhead sequence on the
ROHn pins. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the
FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The
sequence starts on the same high to low transition of the ROHCLKn clock that this
signal is high. This signal is updated at the same time as the ROHCLKn signal
transitions high to low.
This signal can be inverted.
Transmit Line Clock Input
TCLKIn: This clock is typically used for the reference clock for the TOHMIn / TSOFIn,
TFOHn / TSERn, TFOHENIn / TPDENIn, TPDATn, TPDENOn and TSOFOn / TDENn
/ TFOHENOn signals but can also be used as the reference for the TPOSn / TDATn
and TNEGn / TOHMOn signals. This clock is not used when the part is in loop time
mode or the CLAD clocks are used as the transmit clock source.
(PORT.CR3.CLADC)
This input signal can be inverted.
o
o
o
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
CC52: 52 MHz +20 ppm
FUNCTION