DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 318

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.13 FIFO Registers
12.13.1 Transmit FIFO Register Map
The transmit FIFO block has five registers.
Table 12-45. Transmit FIFO Register Map
12.13.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Transmit FIFO Reset (TFRST) – When 0, the Transmit FIFO will resume normal operations, however, data
is discarded until a start of packet/cell is received after RAM power-up is completed. When 1, the Transmit FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the associated TDXA is forced low,
and all incoming data is discarded. If the port was selected when the reset was initiated, the port will be deselected,
and must be reselected (TEN deasserted with address on TADR or TSX asserted with address on TDATA) before
any transfer will occur.
(1,3,5,7)8Ch
(1,3,5,7)8Ah
(1,3,5,7)8Eh
(1,3,5,7)80h
(1,3,5,7)82h
(1,3,5,7)84h
(1,3,5,7)86h
(1,3,5,7)88h
Address
15
--
--
0
7
0
FF.TSRIE
FF.TLCR
FF.TPAC
Register
FF.TSRL
FF.TCR
--
--
--
14
--
--
0
6
0
FIFO Transmit Control Register
FIFO Transmit Level Control Register
FIFO Transmit Port Address Control Register
Unused
FIFO Transmit Status Register Latched
FIFO Transmit Status Register Interrupt Enable
Unused
Unused
FF.TCR
FIFO Transmit Control Register
(1,3,5,7)80h
13
--
--
0
5
0
12
--
0
--
0
4
Register Description
11
--
--
0
3
0
10
--
--
0
2
0
--
--
9
0
1
0
TFRST
--
8
0
0
1