DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 157

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
10.9.3 Transmit Fractional Interface
The Transmit Fractional Interface receives the payload data stream from the ATM/Packet Processor and inserts a
fractional overhead stream.
The incoming fractional overhead stream consists of fractional overhead (TFOHn), input fractional overhead enable
(TFOHENIn), and output fractional overhead enable (TFOHENOn). TFOHn, TFOHENOn and TFOHENIn are
typically referenced to TCLKIn (but also could be referenced to the TLCLKn, TCLKOn/TGCLKn, RCLKOn or
RLCLKn clock pins). If external control is enabled, TFOHENIn marks the fractional overhead periods, and
TFOHENOn is held low. If internal control is enabled, TFOHENOn marks the fractional overhead periods, and
TFOHENIn is ignored. Fractional overhead control is programmable (internal or external). The fractional overhead
source is programmable (all 0's, all 1's, a 10 pattern, or TFOH). See the
FRAC.TCR
Register Definition.
See Section
8.3.3
for specific timing relationships between these pins.
10.9.4 Transmit Fractional Controller
The Transmit Fractional Controller generates the transmit fractional overhead enable output (TFOHENOn) used in
internal control mode to insert fractional overhead. The outgoing transmit data stream to the DS3/E3 Framer is
divided into frames. Each frame is composed of data groups that have a programmable size (1 – 8191 bits). Each
data group is divided into two sections. The first section (Section A) has a programmable size (0 – 8191 bits). The
second section (Section B) contains the remaining bits (g – a bits). See
Figure
10-35. The section that contains
fractional overhead is programmable (Section A or Section B by setting the FRAC.TCR.TSASS register bit).
TFOHENOn is high during the fractional overhead section of the data group, and low during the payload section of
the data group. TFOHENOn is also low during line overhead/stuff periods.
10.9.5 Receive Fractional Interface
The Receive Fractional Interface receives the DS3/E3 payload from the DS3/E3 Framer, and performs fractional
overhead extraction on the payload.
The receive fractional overhead pins are the input fractional overhead enable (RFOHENIn), and the output
fractional overhead enable (RFOHENOn). RFOHENIn is sampled on the rising edge of RCLKOn, typically, or it can
be referenced to the RLCLKn pin. RFOHENOn is updated on the rising edge of RCLKOn (or alternatively the
RLCLKn pin).
If external control is enabled, the receive fractional overhead enable input (RFOHENIn) marks the fractional
overhead bits contained in the DS3/E3 payload. RFOHENIn is high while a fractional overhead period is available
on RSERn. RFOHENIn is low during payload data or line overhead/stuff periods.
If internal control is enabled, the receive fractional overhead enable output (RFOHENOn) marks the fractional
overhead bits in the received DS3/E3 payload. RFOHENOn is high during a fractional overhead bit period on
RSERn. RFOHENOn is low during a payload data or line overhead/stuff period. See Section
8.3.3
for specific
timing relationships between these pins.
10.9.6 Receive Fractional Controller
The Receive Fractional Controller generates the receive fractional overhead enable output (RFOHENOn) used in
internal control mode to extract fractional overhead to the RFOHn pin. The DS3/E3 payload is divided into frames
composed of data groups that have a programmable size (1 – 8191 bits). Each data group is divided into two
sections. The first section (Section A) has a programmable size (a, 0 – 8191 bits). The second section (Section B)
contains the remaining bits (g – a bits). See
Figure
10-35. The section that contains fractional overhead is
programmable (Section A or Section B by setting the FRAC.RCR.RSASS register bit). RFOHENOn is high during
the fractional overhead section of the data group, and low during the payload section of the data group.
RFOHENOn is also low during line overhead/stuff periods.
The first bit of a frame is the first bit of a data group. If a frame does not contain an integer number of data groups (f
/ g is not an integer), the last data group in the frame will be a short data group. The last bit of the short data group
will be the last data period before the start of frame period.