DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 105

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
After a global reset, all of the control and status registers in all ports are set to their default values and all the other
flops are reset to their reset values. The global register GL.CR1.RSTDP, and the port register PORT.CR1.RSTDP
and PORT.CR1.PD bits in all ports, are set after the global reset. A valid initialization sequence would be to clear
the PORT.CR1.PD bits in the ports that are to be active, write to all of the configuration registers to set them in the
desired modes, then clear the GL.CR1.RSTDP and PORT.CR1.RSTDP bits. This would cause the logic in the
ports to start up in a repeatable sequence. The device can also be initialized by clearing the GL.CR1.RSTDP,
PORT.CR1.RSTDP and PORT.CR1.PD them writing to all of the configuration registers to set them in the desired
modes, and clearing all of the latched status bits. The second initialization scheme could cause the device to
temporarily go into modes of operation that were not requested, but will quickly go into the requested modes of
operation.
Some of the IO pins are put in a known state at reset. The global IO pins (GPIO[7:0]) are set as inputs at global
reset.
The
port
output
pins
(TLCLKn,
TPOSn/TDATn,
TNEGn/TOHMOn,
TOHCLKn,
TOHSOFn,
TPOHSOFn/TSOFOn/TDENn/ TFOHENOn, TPOHCLKn/TCLKOn/TGCLKn, ROHn, ROHCLKn, ROHSOFn,
RPOHn/RSERn, RPOHSOFn/RSOFOn/RDENn/RFOHENOn, RPOHCLKn/RCLKOn/RGCLKn) are driven low at
global or port reset and should stay low until after the port power-down PORT.CR1.PD and port data path reset
PORT.CR1.RSTDP bits are cleared.
The system interface tri-state output pins (TDXA[1]/TPXA, TSPA,
RDATA[31:0], RPRTY, RDXA[1]/RPXA/RSX, RSOX, REOP, RVAL, RMOD[1:0], RERR) are high impedance and
the system interface output pins (TDXA[4:2],RDXA[4:2]) are driven low at global reset. The processor port tr8-state
output pins (D[15:0], RDY, INT) are forced into the high-impedance state when the RST pin is active, but not when
the GL.CR1.RST bit is active.
After reset, the device will be in the default configuration: The latched status bits are enabled to be cleared on
write. The CLAD is disabled. The global 8KREF and one-second timers are disabled. The line interface is in B3ZS
mode and the transmit line pins are also disabled. The frame mode is DS3 C-bit with automatic downstream AIS on
LOS or OOF is enabled and automatic RDI on LOF, LOS, SEF or AIS is enabled and automatic FEBE is enabled.
Transmit clock comes from the CLAD CLKA pin. Cell processing is enabled with payload scrambling and HEC
recalculation and Coset addition enabled. The transmit and receive FIFOs are held in reset so no cell traffic will
occur until the FIFOs are configured. The system interface is in 8-bit UTOPIA level 2 with odd parity enabled and
HEC transfer disabled. The pin inversion on all pins is disabled.
Individual blocks are reset and powered down when not used determined by the settings in the line mode bits
PORT.CR2.LM and framer mode bits PORT.CR2.FM[5:0].
10.4 Global Resources
10.4.1 Clock Rate Adapter (CLAD)
The clock rate adapter is used to create multiple clocks for transmit clocks from a single clock reference input on
the CLKA pin. The clock frequency applied to this pin must be at the DS3 (44.736 MHz), E3 (34.368 MHz) and
STS-1 (51.84 MHz) clock rates. Given one of these clocks the other two clocks will be generated. The internally
generated signals can be driven on output pins (CLKB and CLKC) for external use.
The CLAD output is also available as a transmit clock source if selected via the PORT.CR2.CLADC register bit.
The user must supply at least one of the three rates (DS3, E3, STS-1) to the CLKA pin. The CLAD[3:0] bits
informs the PLL of the frequency applied to the pins. Selection of the output clock of the CLAD applied to the
transmitter is controlled by the FM bits (located in PORT.CR2). The CLAD allows maximum flexibility to the user.
The user may supply any of the three clock rates and use the CLAD to convert the rate to the particular clock rate
needed for his application.