DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 69

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-22
Figure 8-22. Internal (IFRAC) Receive Fractional Timing
8.3.4
The Flexible fractional mode provides the capability to modify the payload data from the cell/packet processor
before inserting it into the DS3 or E3 payload. The bit rate of the payload from the cell/packet processor can be
less than the DS3 or E3 payload bit rate. The interface to the DS3 or E3 payload uses the TSOFIn, TSOFOn,
TDENn, TSERn, RSOFOn, RDENn and RSERn pins. The interface to the cell/packet processor uses the
TPDENIn, TPDENOn, TPDATn, RPDENIn and RPDATn pins. The TPDENIn pin is used to determine the bit rate of
the transmit cell/packet payload data. The TPDENOn pin is high when the data on TPDATn is valid. The delay
between TPDENIn and TPDENOn is three clocks. The RPDENIn pin is used to determine the bit rate of the receive
cell/packet processor data. The cell/packet processor uses the cell/packet data on the RPDATn pin when the
RPDENIn pin is high.
Figure 8-23
Figure 8-23. Transmit Flexible Fractional (FFRAC) Timing
RFOHENO
TCLKI or
TPDENO
RCLKI or
TPDENI
TCLKO
TSOFO
TPDAT
RCLKO
RGCLK
TSOFI
TDEN
TSER
RSER
Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing
FPx
P1
shows the timing with the internal fractional transmit port pins
shows the timing with the flexible fractional transmit port pins
X
1
FPy
P2
1
X
2
FPz
P3
2
X
3
FOx
P4
FOH
3
4
FOy
P5
FOH
4
5
FOz
P6
FOH
5
6
OH1
6
X
7
FP1
7
X
8
P14
FP2
8
X
9
FP3
9
10
X
FP4
10
11
X
FP5
P8
11
12
X
FP6
P9
12
13
X
FO1
P10
13
FOH
14
FO2
P11
14
FOH
15
FO3
P12
15
FOH
16
OH2
16
17
X
FP7
17
P13
18
X
FP8
18
19
X
FP9
19
20
X
FP10
20
21
X
FP11
P14
21
22
X
FP12
P15
22
23
X
FO4
P16
23
24
FOH
FO5
P17
FOH
24