DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 338

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 5: Receive Idle Cell Detection Latched (RIDL) – This bit is set when an idle cell is discarded.
Bit 4: Receive Unassigned Cell Detection Latched (RUDL) – This bit is set when an unassigned cell is
discarded.
Bit 3: Receive Invalid Cell Detection Latched (RIVDL) – This bit is set when an invalid cell is discarded.
Bit 2: Receive Errored Header Cell Count Latched (RECCL) – This bit is set when the RECC bit in the CP.RSR
register transitions from zero to one.
Bit 1: Receive Header Pattern Cell Count Latched (RHPCL) – This bit is set when the RHPC bit in the CP.RSR
register transitions from zero to one.
Bit 0: Receive Corrected Header Cell Count Latched (RCHCL) – This bit is set when the RCHC bit in the
CP.RSR register transitions from zero to one.
Register Name:
Register Description:
Register Address/Type:
Bit #
Name
Default
Bit #
Name
Default
Bit 11: Out Of Sync Change Interrupt Enable (OOSIE) – This bit enables an interrupt if the OOSL bit in the
CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 10: Change Of Cell Delineation Interrupt Enable (COCDIE) – This bit enables an interrupt if the COCDL bit
in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 9: Out Of Cell Delineation Change Interrupt Enable (OCDCIE) – This bit enables an interrupt if the OCDCL
bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 8: Loss Of Cell Delineation Change Interrupt Enable (LCDCIE) – This bit enables an interrupt if the LCDCL
bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 7: Receive Errored Header Cell Interrupt Enable (RECIE) – This bit enables an interrupt if the RECL bit in
the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 6: Receive Corrected Header Cell Interrupt Enable (RCHIE) – This bit enables an interrupt if the RCHL bit in
the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RECIE
15
--
0
7
0
RCHIE
14
--
0
6
0
CP.RSRIE
Cell Processor Receive Status Register Interrupt Enable
(1,3,5,7)D2h
RIDIE
13
--
0
5
0
RUDIE
12
--
0
0
4
RIVDIE
OOSIE
11
0
3
0
COCDIE
RECCIE
10
0
2
0
OCDCIE
RHPCIE
9
0
1
0
RCHCIE
LCDCIE
8
0
0
0