DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 176

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

does not match its expected value (up to 2 per frame). A word error increments the count once for each FA word
(both FA1 and FA2) that does not match its expected value (up to 1 per frame).
Parity errors are determined by calculating the BIP-8 (8-Bit Interleaved Parity) of the current E3 frame (overhead
and payload bytes), and comparing the calculated BIP-8 to the EM byte in the next frame. The type of parity errors
accumulated is programmable (bit or block). A bit error increments the count once for each bit in the EM byte that
does not match the corresponding bit in the calculated BIP-8 (up to 8 per frame). A block error increments the
count if any bit in the EM byte does not match the corresponding bit in the calculated BIP-8 (up to 1 per frame).
REI errors are determined by the REI bit (second bit of MA byte). A one indicates an error and a zero indicates no
errors.
The receive defect indication (RDI) alarm is transmitted when the receive framer detects one or more of the
indicated alarm conditions. The RDI bit is not transmitted when all of the indicated alarm conditions are absent.
The RDI bit in the MA byte of the G.832 overhead is set high in the transmit formatter to transmit the alarm. Setting
the receive defect indication on LOS, OOF, LOF, or AIS is individually programmable (on or off).
The receive error indication (REI) bit of the MA byte in the transmit frame will transition from low to high once for
each frame in which a parity error is detected by the receive framer.
10.10.8.9 Receive G.832 E3 Overhead Extraction
Overhead extraction extracts all of the E3 overhead bytes from the G.832 E3 frame. All of the E3 overhead bytes
FA1, FA2, EM, TR, MA, NR, and GC are output on the receive overhead interface (ROH, ROHSOF, and
ROHCLK).
The EM byte is output as an error indication (modulo 2 addition of the calculated BIP-8 and the EM byte.
The TR byte is sent to the receive trail trace controller.
The payload type (third, fourth, and fifth bits of the MA byte) is integrated and stored in a register with change and
unstable indications. The integrated received payload type is also compared against an expected payload type. If
the received and expected payload types do not match (see
Table 10-35. Payload Label Match Status
XXX and YYY equal any value other than 000 or 001; XXX ≠ YYY
The multiframe indicator and timing marker bits (sixth, seventh, and eighth bits of the MA byte) can be integrated
and stored in three register bits or extracted, integrated, and stored in four register bits. The bits (three or four) are
stored with a change indication. The multiframe indicator and timing marker storage type is programmable
(integrated or extracted). When the multiframe indicator and timing marker bits are integrated, the last three bits of
the MA byte are integrated and stored in three register bits. When the multiframe indicator and timing marker bits
are extracted, four timing source indicator bits are transferred in a four-frame multiframe, MSB first. The multiframe
indicator bits (sixth and seventh bits of the MA byte) identify the phase of the multiframe (00, 01, 10, or 11). The
EXPECTED
XXX
XXX
XXX
XXX
000
000
000
001
001
001
RECEIVED
XXX
XXX
XXX
YYY
000
001
000
001
001
000
Mismatch
Mismatch
Mismatch
Mismatch
Mismatch
STATUS
Match
Match
Match
Match
Match
Table
10-35), a mismatch indication is set.
DS3161/DS3162/DS3163/DS3164