DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 63
DS3163
Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3163.pdf
(384 pages)
Specifications of DS3163
Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.3.1.2
There is no suggested time alignment between the RX LINE signals and the RLCLKn clock signal. The RX DATA
signal is not an always readily available signal, it is meant to represent the data value of the other signals.
The RPOSn, RNEGn and RLCLKn pins are available when the line is in B3ZS/HDB3 or AMI mode
The RPOSn and RNEGn signals are sampled at the rising edge of the reference clock signal if the clock pin is not
inverted, otherwise they are sampled at the negative edge. The RLCLKn clock pin is the clock reference used for
the RPOSn and RNEGn signals. The RPOSn and RNEGn pins can be inverted.
Figure 8-3
Figure 8-4. RX Line I/O HDB3 Functional Timing Diagram
8.3.1.3
The TDATn pin is available when the line interface is in the UNI mode and the transmit line pins are enabled. The
TOHMOn and TOHMIn pins are available when the framer is in one of the “- OHM” modes and the transmit line
pins are enabled. The line interface is forced into the UNI mode when the framer is in one of the “- OHM” modes.
The TOHMIn pin is used to control the insertion of gaps in the data by stopping the internal formatters and data
sources. These gaps are inserted where external logic will add more overhead bits to the signal. The TOHMOn
signal is delayed from the TOHMIn signal by three clock periods. The TOHMOn signal aligns to the TDATn signal
and is high when internal framing and signal source has stopped inserting data. The TDATn signal should be
Figure 8-3. RX Line I/O B3ZS Functional Timing Diagram
(RX DATA)
(RX LINE)
(RX DATA)
(RX LINE)
RLCLK
RLCLK
RNEG
RPOS
RPOS
RNEG
RXN
RXP
RXP
RXN
B3ZS/HDB3/AMI Mode Receive Pin Functional Timing
UNI Mode Transmit Pin Functional Timing
and
Figure 8-4
0 V
0 V
BIAS V
BIAS V
+
+
show the relationship between the digital outputs.
-
-
B
B
B
B
B
B
B
B
V
V
V
V
V
V
V
V
HDB3 CODEWORD
B3ZS CODEWORD
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