DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 78

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3163N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Figure 8-32
PHY port 'N' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock
edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device indicates to PHY port 'N' that it is
ready to accept a complete cell transfer by asserting REN. On clock edge 8, PHY port 'N' starts a cell transfer by
placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell.
On clock edge 9, PHY port 'N' de-asserts RSOX as it continues to place additional bytes of the cell on RDAT. On
clock edge 11, the ATM device polls PHY device 'N'. On clock edge 12, PHY port 'M' indicates to the ATM device
that it has a complete cell ready for transfer by asserting RPXA. On clock edge 12, PHY port 'N' indicates to the
ATM device that it does not have a complete cell ready for transfer by de-asserting RPXA. On clock edge 15, the
ATM device deselects PHY port 'N' and selects PHY port 'M' by de-asserting REN and placing PHY port 'M's
address on RADR. On clock edge 16, the ATM device asserts REN. On clock edge 17, PHY port 'N' stops
transferring cell data. On clock edge 18, PHY port 'M' starts a cell transfer by placing the first byte of cell data on
RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY port 'M' de-
asserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 8-32: UTOPIA Level 3 Receive Multiple Cell Transfer Direct Mode
RDXA[2]
RDXA[1]
RDXA[3]
RDXA[4]
RDATA
RSCLK
Cell From:
RADR
Transfer
RSOX
REN
shows a multi-port receive interface multiple cell transfer from different PHY ports. On clock edge 3,
1
2
3
4
5
6
H1
7
H2
8
00h
H3
9
10
P42
11
PORT 1
P43
12
P44
13
P45
14
P46
15
P47
16
P48
17
01h
18
H1
PORT 2
19
H2
20
H3

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