DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 275

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 0: Framing Error Count (FEC) – When 0, the framing error count is zero. When 1, the framing error count is
one or more. The type of framing error event counted is determined by T3.RCR.FECC[1:0]
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: T3 Framing Format Mismatch Latched (T3FML) – This bit is set when the T3FM bit transitions from zero
to one.
Bit 10: Application Identification Channel Change Latched (AICL) – This bit is set when the AIC bit changes
state.
Bit 9: DS3 Idle Signal Change Latched (IDLEL) – This bit is set when the IDLE bit changes state.
Bit 8: Receive Unframed All 1’s Change Latched (RUA1L) – This bit is set when the RUA1 bit changes state.
Bit 7: Out Of MultiFrame Change Latched (OOMFL) – This bit is set when the OOMF bit changes state.
Bit 6: Severely Errored Frame Change Latched (SEFL) – This bit is set when the SEF bit changes state.
Bit 5: Change Of Frame Alignment Latched (COFAL) – This bit is set when the data path frame counters are
updated with a new DS3 frame alignment that is different from the previous DS3 frame alignment.
Bit 4: Loss Of Frame Change Latched (LOFL) – This bit is set when the LOF bit changes state.
Bit 3: Remote Defect Indication Change Latched (RDIL) – This bit is set when the RDI bit changes state.
Bit 2: Alarm Indication Signal Change Latched (AISL) – This bit is set when the AIS bit changes state.
Bit 1: Out Of Frame Change Latched (OOFL) – This bit is set when the OOF bit changes state.
Bit 0: Loss Of Signal Change Latched (LOSL) – This bit is set when the LOS bit changes state.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 11: C-bit Parity Error Latched (CPEL) – This bit is set when a C-bit parity error is detected. This bit is set to
zero in M23 DS3 mode.
Bit 10: Remote Error Indication Latched (FBEL) – This bit is set when a far-end block error is detected. This bit
is set to zero in M23 DS3 mode.
Bit 9: P-bit Parity Error Latched (PEL) – This bit is set when a P-bit parity error is detected.
Reserved
OOMFL
15
15
--
--
7
7
Reserved
SEFL
14
14
--
--
6
6
T3.RSRL1
T3 Receive Status Register Latched #1
(1,3,5,7)28h
T3.RSRL2
T3 Receive Status Register Latched #2
(1,3,5,7)2Ah
Reserved
COFAL
13
13
--
--
5
5
Reserved
LOFL
12
12
--
--
4
4
CPECL
T3FML
CPEL
RAIL
11
11
3
3
FBECL
FBEL
AICL
AISL
10
10
2
2
IDLEL
OOFL
PECL
PEL
9
1
9
1
RUA1L
LOSL
FECL
FEL
8
0
8
0