DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 62

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3 Pin Functional Timing
8.3.1
8.3.1.1
There is no suggested time alignment between the TX LINE signals and the TLCLKn clock signal. The TX DATA
signal is not a readily available signal, it is meant to represent the data value of the other signals.
The TPOSn, TNEGn and TLCLKn signals are available when the line is in B3ZS/HDB3 or AMI mode and the
transmit line pins are enabled.
The TPOSn and TNEGn signals change a small delay after the positive edge of the reference clock if the clock pin
is not inverted; otherwise they change after the negative edge. The TLCLKn clock pin is the clock reference
typically used for the TPOSn and TNEGn signals, but they can be time referenced to the TCLKIn, TCLKOn,
RLCLKn or RCLKOn clock pins. The TPOSn and TNEGn pins can be inverted.
Figure 8-1
Figure 8-1. TX Line I/O B3ZS Functional Timing Diagram
Figure 8-2. TX Line I/O HDB3 Functional Timing Diagram
(TX DATA)
(TX DATA)
(TX LINE)
(TX LINE)
TLCLK
TLCLK
TNEG
TNEG
TPOS
TPOS
Line I/O
TXN
TXN
TXP
TXP
B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing
and
Figure 8-2
0 V
BIAS V
0 V
BIAS V
+
+
show the relationship between the digital outputs.
-
-
B
B
B
B
B
B
B
B
V
V
V
V
V
V
V
V
B3ZS CODEWORD
HDB3 CODEWORD