DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 312

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 10: Receive Z6 Byte Change Latched (RZ6L) – This bit is set when the RZ6[7:0] bits change state (This bit is
zero in E3 mode).
Bit 9: Receive Z5 Byte Change Latched (RZ5L) – This bit is set when the RZ5[7:0] bits change state (This bit is
zero in E3 mode).
Bit 8: Receive Z4 Byte Change Latched (RZ4L) – This bit is set when the RZ4[7:0] bits change state (This bit is
zero in E3 mode).
Bit 7: Receive Z3 Byte Change Latched (RZ3L) – This bit is set when the RZ3[7:0] bits change state.
Bit 6: Receive Z2 Byte Change Latched (RZ2L) – This bit is set when the RZ2[7:0] bits change state.
Bit 5: Receive Z1 Byte Change Latched (RZ1L) – This bit is set when the RZ1[7:0] bits change state.
Bit 4: Receive M2 Byte Change Latched (RM2L) – This bit is set when the RM2[7:0] bits change state.
Bit 3: Receive M1 Byte Change Latched (RM1L) – This bit is set when the RM1[7:0] bits change state.
Bit 2: Receive F1 Byte Change Latched (RF1L) – This bit is set when the RF1[7:0] bits change state.
Bit 1: Receive Link Status Signal Change Latched (LSSL) – This bit is set when the LSS[2:0] bits change state.
Bit 0: Receive Link Status Signal Unstable Change Latched (LSSUL) – This bit is set when the LSSU bit
changes state.
RZ3L
15
--
7
RZ2L
14
--
6
PLCP.RSRL2
PLCP Receive Status Register Latched #2
(1,3,5,7)6Ah
RZ1L
13
--
5
RM2L
12
--
4
RM1L
11
--
3
RZ6L
RF1L
10
2
LSSL
RZ5L
9
1
RZ4L
LSSUL
8
0