DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 315

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Bit 2: Receive F1 Byte Interrupt Enable (RF1IE) – This bit enables an interrupt if the RF1L bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Receive Link Status Signal Interrupt Enable (LSSIE) – This bit enables an interrupt if the LSSL bit is set
and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive Link Status Signal Unstable Interrupt Enable (LSSUIE) – This bit enables an interrupt if the
LSSUL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Framing Error Count (FE[15:0]) – These sixteen bits indicate the number of framing error events on
the incoming PLCP data stream. This register is updated via the PMU signal (see Section 10.4.5).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Parity Error Count (PE[15:0]) – These sixteen bits indicate the number of parity (BIP-8) errors
detected on the incoming PLCP data stream. This register is updated via the PMU signal (see Section 10.4.5).
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
FE15
PE15
FE7
PE7
15
15
0
7
0
0
7
0
FE14
PE14
PE6
FE6
14
14
0
6
0
0
6
0
PLCP.RFECR
PLCP Receive Framing Error Count Register
(1,3,5,7)70h
PLCP.RPECR
PLCP Receive Parity Error Count Register
(1,3,5,7)72h
PE13
FE13
PE5
FE5
13
13
0
5
0
0
5
0
FE12
PE12
FE4
PE4
12
12
0
0
0
0
4
4
PE11
FE11
PE3
FE3
11
11
0
3
0
0
3
0
FE10
PE10
FE2
PE2
10
10
0
2
0
0
2
0
FE9
FE1
PE9
PE1
9
0
1
0
9
0
1
0
PE8
PE0
FE8
FE0
8
0
0
0
8
0
0
0

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