DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 146

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8 DS3/E3 PLCP Framer
10.8.1 General Description
The PLCP Framer de-maps the ATM cells from the DS3/E3 PLCP data stream in the receive direction and maps
ATM cells into the DS3/E3 PLCP data stream in the transmit direction.
The receive direction extracts the PLCP frame from the DS3/E3 data stream, performs frame processing, and
outputs the cells with a beginning of cell indication via the payload interface.
The transmit direction inputs the cells via the payload interface, generates the frame, and inserts the PLCP frame
into the DS3/E3 data stream.
See
Figure 10-29. PLCP Framer Functional Diagram
10.8.2 Features
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DS3 PLCP frame ATM cell extraction and insertion – Accepts a DS3 payload and performs DS3 PLCP
overhead termination and generation.
E3 PLCP frame ATM cell extraction and insertion – Accepts a G.751 E3 payload and performs E3 PLCP
overhead termination and generation.
Generates and detects alarms and errors – In the receive direction, PLCP alarm conditions (OOF, LOF,
COFA, and RAI) and errors (framing, parity, and REI) are detected on the receive signal. In the transmit
direction, alarm conditions and errors can be inserted into the transmit data stream.
Receive overhead extraction port – Extracts all PLCP overhead from the receive signal and outputs it on a
serial interface (RPOH pin).
Externally controlled transmit overhead insertion port – Can insert all PLCP overhead into the transmit
signal from a serial interface. Overhead insertion is fully controlled via the serial overhead interface (TPOH,
TPOHEN, TPOHSOF, TPOHCLK).
Full Duplex serial HDLC channel extraction/insertion – An HDLC channel can be extracted from and/or
inserted into the F1, M1, M2, or M1 and M2 bytes in the PLCP data stream.
Full Duplex serial Trail Trace extraction/insertion – A trail trace can be extracted from and/or inserted into
the F1 byte in the PLCP data stream.
Adapter
Figure 10-29
Clock
Rate
for the location of the PLCP framer in the DS316x devices.
Decoder
Encoder
B3ZS/
HDB3
HDB3
B3ZS/
TUA1
TAIS
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
Transmit
Framer
DS3 / E3
Receive
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
FRAC/
PLCP
TX
RX FRAC/
PLCP
Processor
Processor
Processor
RX BERT
Processor
Tx Packet
TX BERT
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
FIFO
Tx
Rx
FIFO