DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 73

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3163N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Figure 8-27
the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it can
accept cell data by asserting TPXA. On clock edge 4, the ATM device selects PHY device 'N'. On clock edge 5, the
ATM device starts a cell transfer to PHY device 'N' by asserting TEN, placing the first byte of cell data on TDATA,
and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device de-asserts
TSOX as it continues to place additional bytes of the cell on TDATA. On clock edge 6, the ATM device also polls
PHY device 'O'. On clock edge 7, PHY device 'O' indicates that it can accept the transfer of a complete cell. On
clock edge 14, the ATM device polls PHY device 'N'. On clock edge 15, PHY device 'N' indicates that it cannot
accept the transfer of a complete cell. On clock edge 16, the ATM device deselects PHY device 'N' and selects
PHY device 'O' by de-asserting TEN and placing PHY device 'O's address on TADR. On clock edge 17, the ATM
device starts the transfer of a cell to PHY device 'O' by asserting TEN, placing the first byte of cell data on TDATA,
and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device de-
asserts TSOX as it continues to place additional bytes of the cell on TDATA.
Figure 8-27. UTOPIA Level 2 Transmit Multiple Cell Transfer Polled Mode
TDATA
TADR
TSOX
TCLK
TPXA
TEN
Transfer
Cell To:
shows a multi-device transmit interface multiple cell transfer to different PHY devices. On clock edge 2,
M
1
M
1F
2
N
3
1F
N
4
N
5
H1
N
1F
6
H2
O
7
H3
1F
O
8
P42
9
1F
P
10
P43 P44 P45 P46 P47 P48
N
L
11
L
1F M
12
13
M
1F
14
N
15
N
1F
16
O
17
H1
O
1F P
18
H2
O
19
H3
1F
P
20
H4
L

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