DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 19

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.11 Transmit Packet Processor Features
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3.12 Transmit PLCP Formatter Features
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3.13 Transmit DS3/E3 Formatter Features
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3.14 Clock Rate Adapter Features
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Single-bit and multiple-bit header error insertion for diagnostics
Controls include enables/disables/settings for: cell processing, HEC insertion, coset polynomial addition, cell
scrambling, fill cell type, error insertion type/rate/count, HEC bit corruption
Counter for number of cells read from the transmit FIFO
Cell mapping into the DS3/E3 frame, the PLCP frame, an externally defined frame, or the entire line bandwidth
Octet alignment option for externally defined frame formats
FCS calculation (16-bit or 32-bit) and insertion/overwrite
Programmable FCS error insertion for diagnostics
Bit or octet stuffing
Programmable inter-frame fill insertion (flags or all-ones)
Automatic packet abort insertion
Packet scrambling using the self-synchronizing scrambler (x
Controls include enables/disables/settings for: packet processing, FCS insertion or overwrite, 16/32-bit FCS,
inter-frame fill type/length, scrambling, FCS error insertion type/rate/count
Counters for number of packets and bytes read from the transmit FIFO
Octet alignment with octet stuffing option for externally defined frame formats
Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes
Generation of BIP-8 (B1), FEBE and RAI (G1)
C1 cycle/stuff counter generation referenced to GPIO4 input pin, referenced to the received PLCP timing, or
based on an 8 kHz division of one of the clock sources
Automatic or manual insertion of FAS errors, BIP-8 errors
All path overhead fields can be sourced from the PLCP transmit overhead port
HDLC port for data link messages on F1, M1 or M2 bytes
Trail Trace port for trace messages on F1 byte
Insertion of framing overhead for M23 or C-bit parity DS3,or G.751 E3 or G.832 E3
B3ZS/HDB3 encoding
Generation of RDI, AIS, and DS3 idle signal
Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-bit errors,
M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)
HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or
two different codewords back-to-back to send DS3 Line Loopback commands
16-byte Trail Trace Buffer port for the G.832 trail access point identifier
Insertion of G.832 payload type, and timing marker bits from registers
DS3 M23 C bits configurable as payload or overhead; as overhead they can be controlled from registers or the
transmit overhead port
Most framing overhead fields can be sourced from transmit overhead port
Formatter bypass mode for clear channel or externally defined format applications
Support for subrate DS3/E3, internally or externally controlled (Fractional DS3/E3)
Generation of the internally needed DS3 (44.736 MHz), E3 (34.368 MHz), and STS-1(51.84 MHz) clocks a
from single input reference clock
Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz
Derived clocks can be transmitted off-chip for external system use
Standards compliant jitter and wander requirements.
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