DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 246

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.2 Receive Side Line Encoder/Decoder Register Map
The receive side utilizes six registers.
Table 12-26. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map
12.6.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: E3 Code Violation Enable (E3CVE) – When 0, the bipolar violation count will be a count of bipolar
violations. When 1, the bipolar violation count will be a count of E3 line coding violations. Note: E3 line coding
violations are defined as consecutive bipolar violations of the same polarity in ITU O.161. This bit is ignored in
B3ZS mode.
Bit 2: Receive BPV Error Detection Zero Suppression Code Format (REZSF) – When 0, BPV error detection
detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3 signature if two zeros are
followed by a BPV. When 1, BPV error detection detects a B3ZS signature if a zero is followed by a BPV that has
the opposite polarity of the BPV in the previous B3ZS signature, and an HDB3 signature if two zeros are followed
by a BPV that has the opposite polarity of the BPV in the previous HDB3 signature. Note: Immediately after a reset,
this bit is ignored. The first B3ZS signature is defined as a zero followed by a BPV, and the first HDB3 signature is
defined as two zeros followed by a BPV. All subsequent B3ZS/HDB3 signatures will be determined by the setting of
this bit.
Note: The default setting (REZSF = 0) conforms to ITU O.162. The default setting may falsely decode actual BPVs that are not codewords. It is
recommended that REZSF be set to one for most applications. This setting is more robust to accurately detect codewords.
Bit 1: Receive Zero Suppression Decoding Zero Suppression Code Format (RDZSF) – When 0, zero
suppression decoding detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3
signature if two zeros are followed by a BPV. When 1, zero suppression decoding detects a B3ZS signature if a
zero is followed by a BPV that has the opposite polarity of the BPV in the previous B3ZS signature, and an HDB3
signature if two zeros are followed by a BPV that has the opposite polarity of the BPV in the previous HDB3
signature. Note: Immediately after a reset (DRST or RST low), this bit is ignored. The first B3ZS signature is defined
as a zero followed by a BPV, and the first HDB3 signature is defined as two zeros followed by a BPV. All
subsequent B3ZS/HDB3 signatures will be determined by the setting of this bit.
(0,2,4,6)9Ch
(0,2,4,6)9Ah
(0,2,4,6)9Eh
(0,2,4,6)90h
(0,2,4,6)92h
(0,2,4,6)94h
(0,2,4,6)96h
(0,2,4,6)98h
Address
15
--
--
0
7
0
LINE.RBPVCR
LINE.REXZCR
LINE.RSRIE
LINE.RSRL
LINE.RCR
LINE.RSR
Register
--
--
14
--
--
0
6
0
LINE.RCR
Line Receive Control Register
(0.2.4.6)90h
Unused
Line Receive Control Register
Unused
Line Receive Status Register
Line Receive Status Register Latched
Line Receive Status Register Interrupt Enable
Line Receive Bipolar Violation Count Register
Line Receive Excessive Zero Count Register
13
--
--
0
5
0
12
Register Description
--
--
0
0
4
E3CVE
11
--
0
3
0
REZSF
10
--
0
2
0
RDZSF
--
9
0
1
0
RZSD
--
8
0
0
0