DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 214

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 10: Global 8KHz Reference Source [2:0] (G8KRS[2:0]). These bits determine the source for the
internally generated 8 kHz reference as well as the internal one second reference, which is derived from the Global
8 kHz reference. The source is selected from one of the CLAD clocks or from one of the port 8KREF clock sources.
These bits are ignored when the G8KIS bit = 1.
Table 10-10. Global 8kHz Reference Source Table
GL.CR2.
G8KIS
Bit 9: Global 8KHz Reference Output Select (G8KOS). This bit determines whether GPIO2 pin is used for the
global 8KREFO output signal, or is used as specified by GL.GIOCR.GPIO2S[1:0].
Bit 8: Global 8KHz Reference Input Select (G8KIS). This bit determines whether GPIO4 pin is used for the global
8KREFI input signal, or is used as specified by GL.GIOCR.GPIO4S[1:0]. G8KREFI signal will be low if not
selected. Global 8KREF pin signal will be low if not selected.
Bits 3 to 0: CLAD IO Mode [3:0] (CLAD[3:0]). These bits control the CLAD clock IO pins CLKA, CLKB and CLKC.
0
0
0
0
0
0
0
0
1
0 = GPIO2 pin mode selected by GL.GIOCR.GPIO2S[1:0]
1 = GPIO2 is the global 8KREFO output signal selected by GL.CR2.8KRS[2:0]
0 = GPIO4 pin mode selected by GL.GIOCR.GPIO4S[1:0]
1 = GPIO4 is the global 8KREFI input signal for one second timer and ports to use
GL.CR2.
G8KRS[2:0]
000
001
010
011
100
101
110
111
XXX
15
--
--
0
7
0
14
--
--
0
6
0
Source
is disabled. (Note: CLAD is disabled after reset)
disabled
Derived from CLAD STS-1 clock output or CLKC pin if CLAD
is disabled
None, the 8KHZ divider is disabled.
Derived from CLAD DS3 clock output or CLKA pin if CLAD
Derived from CLAD E3 clock output or CLKB pin if CLAD is
Port 1 8KREF source selected by P8KRS[1:0]
Port 2 8KREF source selected by P8KRS[1:0]
Port 3 8KREF source selected by P8KRS[1:0]
Port 4 8KREF source selected by P8KRS[1:0]
GPIO4 pin
GL.CR2
Global Control Register 2
004h
13
--
--
0
5
0
G8KRS2
12
--
0
4
0
G8KRS1
CLAD3
11
0
3
0
G8KRS0
CLAD2
10
0
2
0
G8K0S
CLAD1
9
0
1
0
CLAD0
G8KIS
8
0
0
0