DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 48

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSOFIn /
TOHMIn
TPOHn /
TFOHn /
TSERn /
PIN
TYPE
I
I
Transmit Start Of Frame Input / OH Mask Input
See
TSOFIn: When the port framer is configured for any of the DS3 or E3 non “-OHM”
framed modes, this signal can be used to align the start of the DS3 or E3 frames on
the TSER pin to an external signal. In the fractional mode, the TSOFIn signal can be
used to align the start of frame signal position on the TSERn/TOHn
pin to the rising edge of a signal on this pin. The signal edge does not need to occur
on every frame and can be tied high or low. The signal is sampled on the positive
clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise
it is sampled on the falling edge of the clock. The signal is typically referenced to the
TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,
RCLKOn and RLCLKn clock pins.
This signal can be inverted.
TOHMIn: When the port framer is configured for one of the “- OHM” modes, this
signal is used to mark clock periods when valid data bits are available on the TDATn
output pins. When this signal is low, valid data bits bits will be available on the
TDATn output pins three clock periods later. This signal precedes the signal on
TDATn and TOHMOn by three clock periods. The signal is sampled on the positive
clock edge of the referenced clock pin if the clock pin signal is not inverted, otherwise
it is sampled on the falling edge of the clock. The signal is typically referenced to the
TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,
RCLKOn and RLCLKn clock pins.
This signal can be inverted.
Transmit Serial Data / PLCP Overhead / Fractional Overhead
See
TSERn: When the port framer is configured for Flexible Fractional mode, this pin is
used as the source of the DS3/E3 payload data. The signal is sampled on the
positive clock edge of the referenced clock pin if the clock pin signal is not inverted,
otherwise it is sampled on the falling edge of the clock. The signal is typically
referenced to the TCLKIn transmit clock input pins, but it can be referenced to the
TLCLKn, TCLKOn / TGCLKn, RCLKOn and RLCLKn clock pins
This signal can be inverted.
o
o
o
TPOHn: When the port framer is configured for one of the DS3 or E3 PLCP framing
modes, and the port is enabled, this signal will be used to over-write the DS3 or E3
PLCP framing overhead bits when TPOHENn is active. The TPOHSOFn signal marks
the start of the framing bit sequence. This signal is sampled at the same time as the
TPOHCLKn signal transitions high to low.
This signal can be inverted.
TFOHn: When the port framer is configured for one of the DS3 or E3 internal or
external fractional framing modes, and the port is enabled the internal fractional
framing modes, this pin can be used to source the fractional overhead data. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock
pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The
signal is typically referenced to the TCLKIn transmit clock input pins, but it can be
referenced to the TLCLKn, TCLKOn / TGCLKn, RCLKOn and RLCLKn clock pins
This signal can be inverted.
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
Table 10-18.
Table 10-19.
FUNCTION