DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 101

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-6. Transmit Framer Pin Signal Timing Source Select
10.2.3.3 Receive Line Interface Pin Timing Source Selection
(RPOSn/RDATn, RNEGn/RLCVn/ROHMIn)
The receive line interface signal pin group must be clocked in with the RLCLK clock input pin.
10.2.3.4 Receiver Framer and Fractional Pin Timing Source Selection
(RSERn, RSOFOn/RDENn/RFOHENOn, RFOHENIn/RPDENIn, RPDATn)
The receive framer and fractional signal pin group has the same functional timing clock source as the RCLKOn pin
described in
Other clock pins can be used for the external timing. The RCLKOn receive clock output pin is always a valid output
clock for external logic to use for these signals when PORT.CR3.RFTS=0.
The receive framer and fractional timing select bit (RFTS) is used to select input or output clock pin timing. When
RFTS=0, output clock timing is selected. When RFTS=1, input clock timing is selected. If RFTS is set for input
clock timing and an output clock pin is used, or if RFTS is set for output clock timing and an input clock pin is used,
then the setup, hold and delay timings, as specified in
of RFTS=1 and other modes in which there is no input clock pin available for external timing since the clock source
is derived internally from the CLAD.
Table 10-7. Receive Framer Pin Signal Timing Source Select
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
DLB (100) or LLB&DLB(110)
DLB (100) or LLB&DLB(110)
not LLB, DLB or PLB (00X)
not LLB, DLB or PLB (00X)
PLB (011) or DLB (100) or
PLB (011) or DLB (100) or
Table
not LLB&DLB(110)
not DLB (100) and
DLB&LLB (110)
DLB&LLB (110)
not PLB (011)
not PLB (011)
10-4.
LBM[2:0]
ALB(001)
LLB (010)
LBM[2:0]
ALB(001)
PLB (011)
LLB (010)
XXX
XXX
XXX
XXX
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
0
1
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
Table
RCLKOn, TCLKOn
RCLKOn, TLCLKn
RCLKOn
No valid timing to any input clock pin
TCLKIn
Valid Timing to These Clock Pins
RCLKOn, TLCLKn, TCLKOn
RLCLKn
RCLKOn, TLCLKn, TCLKOn
RLCLKn
Valid Timing to These Clock Pins
TCLKOn, TLCLKn, RCLKOn
RLCLKn
TCLKOn, TLCLKn, RCLKOn
TCLKOn, RCLKOn
TCLKOn
TCLKOn, TLCLKn
No valid timing to any input clock pin
TCLKIn
RLCLKn
18-1, will not be valid. There are some combinations