DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 177

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
timing marker bit (eighth bit of the MA byte) contains the timing source indicator bit indicated by the multiframe
indicator bits (first, second, third, or fourth bit respectively). The four timing source indicator bits are extracted from
the multiframe, integrated, and stored in four register bits with unstable and change indications.
The NR byte is integrated and stored in a register along with a change indication, it is sent to the receive FEAC
controller, and it can be sent to the receive HDLC controller. The byte sent to the receive HDLC controller is
programmable (NR or GC).
The GC byte is integrated and stored in a register along with a change indication, and can be sent to the receive
HDLC controller. The byte sent to the receive HDLC controller is programmable (NR or GC).
10.10.8.10 Receive G.832 Downstream AIS Generation
Downstream G.832 E3 AIS can be automatically generated on an OOF, LOS, or AIS condition or manually
inserted. If automatic downstream AIS is enabled, downstream AIS is inserted when an LOS, OOF, or AIS
condition is declared. Automatic downstream AIS is programmable (on or off). If manual downstream AIS insertion
is enabled, downstream AIS is inserted. Manual downstream AIS insertion is programmable (on or off).
Downstream AIS is removed when all OOF, LOS, and AIS conditions are terminated and manual downstream AIS
insertion is disabled. RPDT will be forced to all ones during downstream AIS.
10.10.9 Clear-Channel Frame Processor
10.10.9.1 Transmit Clear-Channel AIS Generation
Clear-channel AIS generation overwrites the data stream with AIS. If transmit AIS is enabled, the data stream
(payload) is forced to all ones.
10.10.9.2 Receive Clear-Channel Performance Monitoring
Performance monitoring checks the clear-channel signal for alarm conditions. The alarm conditions detected are
LOS and RUA1. A Loss Of Signal (LOS) condition is declared when the B3ZS/HDB3 encoder is active, and it
declares an LOS condition. A LOS condition is terminated when the B3ZS/HDB3 encoder is inactive, or it
terminates an LOS condition.
A Receive Unframed All 1’s (RUA1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less
zeros are detected. A RUA1 condition is terminated if in each of 4 consecutive 2047 bit windows, six or more zeros
are detected.
10.10.9.3 Receive Clear-channel Downstream AIS Generation
Downstream clear-channel AIS can be automatically generated on an LOS condition or manually inserted. If
automatic downstream AIS is enabled, downstream AIS is inserted when an LOS condition is declared. Automatic
downstream AIS is programmable (on or off). If manual downstream AIS insertion is enabled, downstream AIS is
inserted. Manual downstream AIS insertion is programmable (on or off). Downstream AIS is removed when all LOS
conditions are terminated and manual downstream AIS insertion is disabled. All bits will be forced to ones during
downstream AIS.
10.11 HDLC Overhead Controller
10.11.1 General Description
The DS316x devices contain built-in HDLC controllers (one per port) with 256-byte FIFOs for insertion/extraction of
DS3 PMDL, G.751 Sn bit and G.832 NR/GC bytes and PLCP NR/GC bytes
The HDLC Overhead Controller de-maps HDLC overhead packets from the DS3/E3 data stream in the receive
direction and maps HDLC packets into the DS3/E3 data stream in the transmit direction.
The receive direction performs packet processing and stores the packet data in the FIFO. It removes packet data
from the FIFO and outputs the packet data to the microprocessor via the register interface.
The transmit direction inputs the packet data from the microprocessor via the register interface and stores the
packet data in the FIFO. It removes the packet data from the FIFO and performs packet processing.