DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 12

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
Table 11-1. Global and Test Register Address Map ............................................................................................... 195
Table 11-2. Per Port Register Address Map............................................................................................................ 196
Table 12-1. Global Register Bit Map........................................................................................................................ 197
Table 12-2. System Interface Bit Map ..................................................................................................................... 198
Table 12-3. Port Register Bit Map ........................................................................................................................... 198
Table 12-4. BERT Register Bit Map ........................................................................................................................ 199
Table 12-5. Line Register Bit Map ........................................................................................................................... 200
Table 12-6. HDLC Register Bit Map ........................................................................................................................ 200
Table 12-7. FEAC Register Bit Map ........................................................................................................................ 201
Table 12-8. Trail Trace Register Bit Map................................................................................................................. 202
Table 12-9. T3 Register Bit Map.............................................................................................................................. 202
Table 12-10. E3 G.751 Register Bit Map................................................................................................................. 203
Table 12-11. E3 G.832 Register Bit Map................................................................................................................. 204
Table 12-12. Clear-Channel Register Bit Map......................................................................................................... 205
Table 12-13. Fractional Register Bit Map ................................................................................................................ 205
Table 12-14. PLCP Register Bit Map....................................................................................................................... 206
Table 12-15. FIFO Register Bit Map........................................................................................................................ 207
Table 12-16. Transmit Cell Processor Register Bit Map ......................................................................................... 208
Table 12-17. Transmit Packet Processor Register Bit Map .................................................................................... 208
Table 12-18. Receive Cell Processor Register Bit Map .......................................................................................... 209
Table 12-19. Receive Packet Processor Register Bit Map ..................................................................................... 210
Table 12-20. Global Register Map........................................................................................................................... 211
Table 12-21. Transmit System Interface Register Map ........................................................................................... 220
Table 12-22. Receive System Interface Register Map ............................................................................................ 221
Table 12-23. Per Port Common Register Map ........................................................................................................ 224
Table 12-24. BERT Register Map............................................................................................................................ 236
Table 12-25. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 245
Table 12-26. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 246
Table 12-27. Transmit Side HDLC Register Map .................................................................................................... 250
Table 12-28. Receive Side HDLC Register Map ..................................................................................................... 254
Table 12-29. FEAC Transmit Side Register Map .................................................................................................... 258
Table 12-30. FEAC Receive Side Register Map ..................................................................................................... 261
Table 12-31. Transmit Side Trail Trace Register Map............................................................................................. 264
Table 12-32. Trail Trace Receive Side Register Map.............................................................................................. 266
Table 12-33. Transmit DS3 Framer Register Map .................................................................................................. 270
Table 12-34. Receive DS3 Framer Register Map ................................................................................................... 272
Table 12-35. Transmit G.751 E3 Framer Register Map .......................................................................................... 280
Table 12-36. Receive G.751 E3 Framer Register Map ........................................................................................... 282
Table 12-37. Transmit G.832 E3 Framer Register Map .......................................................................................... 287
Table 12-38. Receive G.832 E3 Framer Register Map ........................................................................................... 290
Table 12-39. Transmit Clear-Channel Register Map............................................................................................... 298
Table 12-40. Receive Clear-Channel Register Map................................................................................................ 299
Table 12-41. Fractional Transmit Side Register Map .............................................................................................. 301
Table 12-42. Receive Side Register Map................................................................................................................ 303
Table 12-43. Transmit Side PLCP Register Map .................................................................................................... 305
Table 12-44. Receive Side PLCP Register Map ..................................................................................................... 309
Table 12-45. Transmit FIFO Register Map.............................................................................................................. 318
Table 12-46. Receive FIFO Register Map............................................................................................................... 322
Table 12-47. Transmit Cell Processor Register Map............................................................................................... 325
Table 12-48. HEC Error Mask ................................................................................................................................. 329
Table 12-49. Receive Cell Processor Register Map................................................................................................ 333
Table 12-50. Transmit Packet Processor Register Map.......................................................................................... 345
Table 12-51. Receive Packet Processor Register Map........................................................................................... 350
Table 13-1. JTAG Instruction Codes ....................................................................................................................... 364
Table 13-2. JTAG ID Codes .................................................................................................................................... 365
Table 14-1. Pin Assignment Breakdown ................................................................................................................. 366
Table 17-1. Recommended DC Operating Conditions ............................................................................................ 372