DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 185

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-47. FEAC Controller Block Diagram
10.13.2 Features
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10.13.3 Functional Description
The bits in a code are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB
last. The bits in a code in an incoming signal are numbered in the order they are received, 1 (MSB) to 6 (LSB).
However, when a code is stored in a register, the MSB is stored in the lowest numbered bit (0), and the LSB is
stored in the highest numbered bit (5). This is to differentiate between a code in a register and the corresponding
code in a signal.
10.13.3.1 Transmit Data Storage
The Transmit Data Storage block contains the registers for two FEAC codes (C{1:6]) and controller circuitry for
reading and writing the memory. The Transmit Data Storage receives data from the microprocessor interface, and
stores the data in memory. The Transmit FEAC Processor reads the data from the Transmit Data Storage.
10.13.3.2 Transmit FEAC Processor
The Transmit FEAC Processor accepts data from the Transmit Data Storage performs FEAC processing. The
FEAC codes are read from Transmit Data Storage with the MSB (C[1]) in TFCA[0] or TFCB[0], and the LSB (C[6])
in TFCA[5] or TFCB[5].
FEAC processing has four modes of operation (Idle, single code, dual code, and continuous code). In Idle mode, all
ones are output on the outgoing FEAC data stream. In single code mode, the code from TFCA[5:0] is inserted into
a codeword (see
are output. In dual code mode, the code from TFCA[5:0] is inserted into a codeword, and sent ten consecutive
times. Then the code from TFCB[5:0] is inserted into a codeword, and sent 10 consecutive times. Once both
codewords have both been sent 10 times, all ones are output. In continuous mode, the code from TFCA[5:0] is
inserted into a codeword, and sent until the mode is changed
Programmable dual codeword output – The transmit side can be programmed to output a single codeword
ten times, one codeword ten times followed by a second codeword ten times, or a single codeword
continuously.
Four codeword receive FIFO
Fully independent transmit and receive paths
Fully independent Line side and register side timing – The FIFO can be read from or written to at the
register interface side while all line side clocks and signals are inactive, and read from or written to at the line
side while all register interface side clocks and signals are inactive.
Adapter
Clock
Rate
Figure
10-48), and sent 10 consecutive times. Once the 10 codewords have been sent, all ones
Encoder
Decoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
Transmit
Receive
Framer
DS3 / E3
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
FRAC/
PLCP
TX
RX FRAC/
PLCP
Processor
Processor
RX BERT
Processor
Processor
TX BERT
Tx Packet
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
FIFO
Tx
Rx
FIFO