DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 61

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AVDDC
JTRST
CLKC
CLKA
CLKB
VDD
VSS
PIN
TYPE
PWR
PWR
PWR
Ipu
IO
IO
I
JTAG Reset (active low with pullup)
JTRST: This input forces the JTAG controller logic into the reset state and forces the
JTDO pin into high impedance when low. This pin should be low while power is
applied and set high after the power is stable. The pin can be driven high or low for
normal operation, but must be high for JTAG operation.
Clock A
CLKA: This clock input is a DS3 signal (44.736MHz ±20ppm) when the CLAD is
disabled or it is one of the CLAD reference clock signals when the CLAD is enabled.
Clock B
CLKB: This pin is a E3 (34.368 MHz ±20ppm) input signal when the CLAD is disabled
or it can be enabled to output a generated clock when the CLAD is enabled. The pin
is driven low when it is not selected to output a clock signal and the CLAD is enabled.
Refer to
Clock C
CLKC: This pin is a STS-1 (51.84 MHz ±20ppm) input signal when the CLAD is
disabled or it can be enabled to output a generated clock when the CLAD is enabled.
The pin is driven low when it is not selected to output a clock signal and the CLAD is
enabled. Refer to
Ground, 0V potential
Common to digital core, digital IO and all analog circuits.
Digital 3.3V
Common to digital core and digital IO.
Analog 3.3V for CLAD
Powers clock rate adapter common to all ports.
Table
10-9.
Table
10-9.
POWER
CLAD
FUNCTION