DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 379
![IC TRPL ATM/PACKET PHY 400-PBGA](/photos/6/87/68748/400-bga_21-0306_sml.jpg)
DS3163
Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3163.pdf
(384 pages)
Specifications of DS3163
Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 18-6. System Interface Level 3 Timing
(V
RSCLK and TSCLK
RSCLK and TSCLK
RSCLK and TSCLK
RADR and REN
RADR and REN
RDATA, RPRTY,
RPXA, RSOX, REOP,
RVAL, RMOD, and
RERR
TDATA, TPRTY,
TADR, TEN, TSOX,
TEOP, TMOD, and
TERR
TDATA, TPRTY,
TADR, TEN, TSOX,
TEOP, TMOD, and
TERR
TPXA and TSPA
Note 1:
Note 2:
Note 3:
DD
SIGNAL NAME(S)
= 3.3V ±5%, T
The input/output timing reference level for all signals is VDD/2.
Rise and fall times are measured at output side with the output unloaded. Rise time is measured from 20% to 80% V
is measured from 80% to 20% V
These times are met with a 30pF, 300 Ω load on the associated output pin.
j
= -40°C to +125°C.)
SYMBOL
t2/t1
f1
t3
t5
t6
t7
t5
t6
t7
Clock Duty Cycle
Rise/Fall Times
Hold Time from RSCLK
Setup Time to RSCLK
Delay from RSCLK
Hold Time from TSCLK
Setup Time to TSCLK
OH
Clock Frequency (1/t1)
Delay from TSCLK
.
DESCRIPTION
MIN TYP
3.5
3.5
40
0
0
2
0
2
50
MAX
9.5
9.5
66
60
2
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
%
OH
. Fall time
NOTES
1,2
1,3
1,3
1
1
1
1
1
1
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