DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 229

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 13: Receive Clock Output Select (RCLKS). This bit is used to select the function of the RPOHCLKn /
RGCLKn / RCLKOn pins. See
Bit 12: Receive Start Of Frame Output Select (RSOFOS). This bit is to select the function of the RSOFOn /
RDENn pins. See
Bit 11: Receive PLCP/Fractional Port Enable (RPFPE). This bit is used to enable the receive PLCP/Fractional
port pins. See tables in section 10.5.9.2.
Bit 10: Transmit Clock Output Select (TCLKS). This bit is used to select the function of the TPOHCLKn /
TGCLKn / TCLKOn pins. See
Bit 9: Transmit Start Of Frame Output Select (TSOFOS). This bit is used to select the function of the TSOFOn /
TDENn pins. See
Bit 8: Transmit PLCP/Fractional Port Enable (TPFPE). This bit is used to enable the transmit PLCP/fractional
port pins. See tables in section 10.5.9.1.
Bits 7 and 6: Port 8 kHz Reference Source Select [1:0] (P8KRS[1:0]). These bits select the source of the 8
kHz reference from the port sources. The 8K reference for this port can be used as the global 8K reference source.
See
Table 10-11. Port 8kHz Reference Source Table
PORT.CR3.P8KRS[1:0]
Bit 5: Port 8 kHz Reference Source (P8KREF). This bit selects the source of the 8 kHz reference for PLCP
trailer operation and one-second timer.
Table 10-11.
0 = Selects the RGCLKn signal, RPOHCLKn signal, or the drive low pin function.
1 = Selects RCLKOn signal.
0 = Selects RDENn signal.
1 = Selects RSOFOn signal.
0 = Disable receive PLCP/Fractional port pins
1 = Enable receive PLCP/Fractional port pins
0 = Selects TGCLKn or TPOHCLKn signal.
1 = Selects TCLKOn signal.
0 = Selects TDENn signal.
1 = Selects TSOFOn signal.
0 = Disable transmit PLCP/Fractional port pins
1 = Enable transmit PLCP/Fractional port pins
0 = 8 kHz reference from global source
1 = 8 kHz reference from this ports selected source
0X
10
11
P8KRS1
15
--
0
7
0
Table 10-21.
Table
10-28.
P8KRS0
14
Source
Receive PLCP 8kHZ output
Receive RLCLKn pin
Transmit internal framer clock (based on TCLKIn
pin or CLAD clock)
--
0
6
0
Table
Table
PORT.CR3
Port Control Register 3
(0,2,4,6)44h
10-22.
10-29.
P8KREF
RCLKS
13
0
5
0
RSOFOS
LOOPT
12
0
0
4
RPFPE
CLADC
11
0
3
0
TCLKS
RFTS
10
0
2
0
TSOFOS
TFTS
9
0
1
0
TPFPE
TLTS
8
0
0
0