DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 102

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.4 Clock Structures On Signal IO Pins
The signals on the input pins (RFOHENIn, TOHMIn/TSOFIn, TFOHn/TSERn, TFOHENIn) can be used with any of
the clock pins for setup/hold timing on clock input and output pins. There will be a flop at each input whose clock is
connected to the signal from the input or output clock source pins with as little delay as possible from the signal on
the clock IO pins. This means using the input clock signal before the delays of the internal clock tree to clock the
input signals, and using the output clock signals used to drive the output clock pins to clock the input signals.
The signals on the output pins (TPOSn/TDATn, TNEGn/TOHMOn, TSOFOn/TDENn/TFOHENOn, RSERn,
RSOFOn/RDENn/RFOHENOn) can be used with any of the clock sources for delay timing. There will be a flop at
each output whose clock is connected to the signal from the input or output clock source pins with as little delay as
possible from the signal on the clock I/O pins. This means using the input clock signal before the delays of the
internal clock tree to clock the input signals, and using the output clock signals to drive the output clock pins to
clock the input signals.
10.2.5 Gapped Clocks
The transmit and receive output clocks can be gapped in certain configurations. See
for the configuration settings. The gapped clocks are active during DS3 or E3 framed payload bits or DS3 or E3
fractional overhead bits depending on which mode the device is configured for.
In the internal DS3 or E3 fractional modes, the transmit gapped clock is created by the logical OR of the TCLKOn
and TFOHENOn signals creating a positive or negative clock edge for each fractional overhead bit, the receive
gapped clock is created by the logical OR of the RCLKOn and RFOHENOn signals. In the internal DS3 or E3 non-
fractional modes, the transmit gapped clock is created by the logical OR of the TCLKOn and TDENn signals
Figure 10-3. Example I/O Pin Clock Muxing
TSER
TCLKI
RLCLK
CLAD CLOCKS
STS-1 CLK
DS3 CLK
E3 CLK
PIN INVERT
PIN INVERT
PIN INVERT
DELAY
TFTS
0
1
CLOCK TREE
CLOCK TREE
CLOCK TREE
INTERNAL
INTERNAL
INTERNAL
SIGNAL
SIGNAL
SIGNAL
D
SET
CLR
Q
Q
D
D
D
D
SET
CLR
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
Q
Q
INTERNAL
SIGNAL
DELAY
DELAY
DELAY
TFTS
TLTS
RFTS
0
1
0
1
0
1
D
D
D
CLR
SET
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
RCLKO
TCLKO
TLCLK
TDEN
RSER
TPOS
Table 10-22
and
Table 10-29