DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 144

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3161/DS3162/DS3163/DS3164
In packet processing mode, all operations are byte based. The Transmit FIFO is considered empty when its
memory does not contain any data. The Transmit FIFO is considered "almost empty" when its memory does not
contain a packet end and there is a programmable number of bytes or less stored in the memory. The Transmit
FIFO is considered "almost full" when its memory has a programmable number of bytes or less available for
storage. When the Transmit FIFO has more bytes available for storage than the “almost full” level the TDXA[n] or
TPXA pin will be asserted to signal to the POS device that it is ready to receive more packet data. The Transmit
FIFO is considered full when it does not have any space available for storage. When the Transmit FIFO is full, the
TDXA[n] pin will be de-asserted. The Transmit FIFO accepts data from the Transmit System Interface Bus
Controller until full. If a start of packet or short packet (32-bit data word with a start of packet and end of packet) is
received while full, the data is discarded and a FIFO overflow condition is declared. If any other packet data is
received while full, the current packet being transferred is marked with an abort indication, and a FIFO overflow
condition is declared. Once a FIFO overflow condition is declared, the Transmit FIFO will discard data until a start
of packet is received while the FIFO has more space available than the "almost full" level. If a packet error (a
transfer with TERR and TEOP asserted) is received from the Transmit System Interface Bus Controller, an aborted
transfer is declared, the data is stored in memory with a packet abort indication, and the Transmit FIFO will discard
data until a start of packet is received. If an end of a packet has been received and the Transmit FIFO receives
packet data other than a start of packet, an invalid transfer is declared, and all packet data is discarded until a start
of packet is received. If a start of packet is received before a previous packet transfer has been completed (an end
of packet was never received), the current packet being transferred is marked with an abort indication and a short
transfer is declared. The new packet is processed normally. If the Transmit Packet Processor attempts a read while
the Transmit FIFO is empty, a FIFO underflow condition is declared. Once a FIFO underflow condition is declared,
the Transmit FIFO data will be discarded until a start of cell is received.
10.7.7.2 Receive FIFO
The Receive FIFO block contains memory for 64 32-bit data words. The Receive FIFO separates the receive
system interface timing from the receive physical interface timing. The Receive FIFO functions include filling the
memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory
overflow and underflow conditions. The Receive FIFO port address used for selection and polling by the Receive
System Interface Bus Controller is programmable. In system loopback, data is looped back from the Transmit FIFO
to the Receive FIFO.
In cell processing mode, all operations are cell based. The Receive FIFO is considered empty unless it contains a
cell. The Receive FIFO is considered "almost empty" when it contains a programmable number of cells or less.
When the Receive FIFO level has more data available for transfer than the “almost empty” level, the RDXA[n] pin is
asserted. The Receive FIFO is considered "almost full" when it does not have space available to store a complete
cell. The Receive FIFO is considered full when it does not have any space available. The Receive FIFO accepts
cell data from the Receive Cell Processor until full. If cell data is received while the FIFO is full, the cell is discarded
and a FIFO overflow condition is declared. Once a FIFO overflow condition is declared, the Receive FIFO will
discard cell data until a cell start is received while the FIFO has space available to store a complete cell. If the
Receive System Interface Bus Controller attempts a read while the FIFO is empty, the read is ignored.
In packet processing mode, all operations are 32-bit word based. The Receive FIFO is considered empty when it
does not contain any data. The Receive FIFO is considered "almost empty" when its memory does not contains a
packet end and there is a programmable number of words or less stored in the memory. When the Receive FIFO
has more bytes available for transfer than the “almost empty” level or has an end of packet, the RDXA[n] pin is
asserted (POS-PHY Level 2). The Receive FIFO is considered "almost full" when its memory has a programmable
number of words or less available for storage. The Receive FIFO is considered full when it does not have any
space available for storage. The Receive FIFO accepts data from the Receive Packet Processor until full. If a
packet start or short packet is received while full, the data is discarded and a FIFO overflow condition is declared. If
any other packet data (packet end or middle) is received while full, the current packet being transferred is marked
with an abort indication, and a memory overflow condition is declared. Once a memory overflow condition is
declared, the Receive FIFO will discard data until a packet start is received while the FIFO has more space
available than the "almost full" level. If the Receive System Interface Bus Controller attempts a read while the FIFO
is empty, the read is ignored.