DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 83

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-37
2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS device that it has a block
of packet data or an end of packet ready for transfer by asserting RPXA. On clock edge 4, the POS device selects
PHY port 'N'. On clock edge 5, the POS device indicates to PHY port 'N' that it is ready to accept a block of packet
data by placing its address on RADR and asserting REN. On clock edge 6, PHY port 'N' starts packet transfer by
asserting RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first
transfer of the packet. On clock edge 7, PHY port 'N' de-asserts RSOX as it leaves RVAL asserted and continues
to place additional bytes of the packet on RDATA. On clock edge 14, PHY port 'N' places the last byte of the packet
on RDATA, and asserts REOP to indicate that this is the last transfer of the packet. On clock edge 15, PHY port 'N'
de-asserts RVAL and REOP ending the packet transfer process. On clock edge 16, the POS device de-asserts
REN and selects PHY port 'P'. On clock edge 17, PHY port 'N' tri-states its RVAL, RDATA, RSOX, REOP, and
RERR outputs and the POS device indicates to PHY port 'P' that it is ready to accept a block of packet data by
placing its address on RADR and asserting REN. On clock edge 18, PHY port 'P' starts packet transfer by asserting
RVAL, placing the first byte of the packet on RDATA, and asserting RSOX to indicate that this is the first transfer of
the packet. On clock edge 19, PHY port 'P' de-asserts RSOX as it leaves RVAL asserted and continues to place
additional bytes of the packet on RDATA. While this example shows a different PHY port ('P') being selected for the
next packet transfer, the timing is identical if the same PHY port ('N') is chosen for the next packet transfer.
Figure 8-37. POS-PHY Level 2 Receive Multiple Packet Transfer (Polled Status Mode)
From PHY
Transfer
RADR
RSOX
RERR
REOP
RPXA
RDAT
RCLK
RVAL
REN
shows a multi-device receive interface in packet transfer mode multiple packet transfer. On clock edge
1
1F
M
2
N
3
1F
N
4
N
5
1F
N
6
P1
O
7
1F
P2
O
8
P3
P
9
1F
P4
P
10
…
…
N
11
P61
1F
L
12
P62
M
13
P63
1F
M
14
P64
O
15
1F
O
X
16
X
P
17
1F
P
18
P1
L
19
P
1F
P2
L
20
P3
M