DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 226

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 9: BERT Enable (BENA). This bit is used to enable the transmit and receive BERT logic. The BERT pattern
will be the payload data replacing the cell or packet data from the system interface.
Note: Data on the receive side will flow to the Cell/Packet processor regardless of the setting of BENA. The packet
processor could detect packets even if not desired. To disable possible packets on the system interface, set the
FIFO.RCR.RFRST bit.
Bit 8: HDLC Select (HDSEL). This bit is used to select the source of the receive HDLC controller and the
destination of the transmit HDLC controller when in DS3 or E3 PLCP mode. When not in any PLCP mode, this bit
has no meaning and the HDLC controllers are connected to the DS3 or E3 framers if in DS3 or E3 mode.
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used to insert errors in all error insertion logic configured to
use this bit when PORT.CR1.MEIM=0. The error(s) will be inserted when this bit is toggled low to high.
Bit 6: Transmit Manual Error Insert Mode (MEIM). These bits select the method transmit manual error insertion
for this port for error generators configured to use the external TMEI signal. The global updates are controlled by
the GL.CR1.MEIMS bit.
Bit 4: Performance Monitor Update Mode (PMUM). These bits select the method of updating the performance
monitor registers. The global updates are controlled by the GL.CR1.GPM[1:0] bits.
Bit 3: Performance Monitor Register Update (PMU) This bit is used to update all of the performance monitor
registers configured to use this bit when PORT.CR1.PMUM=0. The performance registers configured to use this
signal will be updated with the latest count value and the counters reset when this bit is toggled low to high. The bit
should remain high until the performance register update status bit (PORT.SR.PMS) goes high, then it should be
brought back low which clears the PMS status bit.
Bit 2: Power-Down (PD). When this bit is set, the digital logic for this port are powered down and considered “out
of service”. The logic is powered down by stopping the clocks. See the
Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers, in this port
to their default state. This bit must be set high for a minimum of 100ns and then set back low. See the
Power-Down
be set to one).
Bit 0: Reset (RST). When this bit is set, it will force all the internal data path and status and control registers
(except this RST bit) of this port to their default state. See the
be set high for a minimum of 100ns and then set back low. This software bit is logically OR’ed with the inverted
hardware signal RST and the GL.CR1.RST bit.
0 = BERT logic disabled and powered down
1 = BERT logic enabled
0 = Connect HDLC controller to DS3 or E3 framers
1 = Connect HDLC controller to PLCP framers
0 = Port software update via PORT.CR1.TMEI
1 = Global update source
0 = Port software update
1 = Global update
0 = Normal operation
1 = Power-down port circuits (default state)
0 = Normal operation
1 = Force all data path registers to their default values
0 = Normal operation
1 = Force all internal registers to their default values
Section 10.3. Note: The Default State of this bit is 1 (after a general reset (port or global), this bit will
Reset and Power-Down
Reset and Power-Down
Section 10.3. This bit must
Section 10.3.
Reset and