DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 76

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.5.2
Figure 8-30
indicate to the ATM device that they can accept cell data by asserting the TDXA[n]. On clock edge 2, the ATM
device selects PHY port '1' by putting address ‘00h’ on the address bus. On clock edge 5, the ATM device starts a
cell transfer to PHY port '1' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to
indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device de-asserts TSOX as it continues
to place additional bytes of the cell on TDATA. On clock edge 13, PHY port ‘2’ asserts TDXA[2] to indicate it is
ready to accept a cell. On clock edge 15, PHY port ‘1’ deasserts TDXA[1] to indicate to the ATM device that it does
not have the availability to receive another complete cell. On clock edge 16, the ATM device selects PHY port '2'
by de-asserting TEN and placing PHY port '2's address on TADR. On clock edge 17, the ATM device starts the
transfer of a cell to PHY port '2' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX
to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device de-asserts TSOX as it
continues to place additional bytes of the cell on TDATA.
Figure 8-30. UTOPIA Level 3 Transmit Multiple Cell Transfer Direct Mode
TDXA[2]
TDXA[1]
TDXA[3]
TDXA[4]
TDATA
TSCLK
TADR
Transfer
Cell To:
TSOX
TEN
UTOPIA Level 3 Functional Timing
shows a multi-port transmit interface multiple cell transfer to different PHY devices. PHY port '1', ‘3’, ‘4’
1
2
3
4
5
H1
6
H2
7
H3
…
8
00h
9
P42
10
PORT 1
P43
11
P44
12
P45
13
P46
14
P47
15
P48
16
17
H1
01h
18
PORT 2
H2
19
H3
20
H4