DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 182

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-45. Trail Trace Controller Block Diagram
10.12.2 Features
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10.12.3 Functional Description
The bits in a byte are received most significant bit (MSB) first and least significant bit (LSB) last. When they are
output serially, they are output MSB first and LSB last. The bits in a byte in an incoming signal are numbered in the
order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the
highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a
byte in a register and the corresponding byte in a signal.
10.12.4 Transmit Data Storage
The Transmit Data Storage block contains memory for 16 bytes of data and controller circuitry for reading and
writing the memory. The Transmit Data Storage controller functions include filling the memory and maintaining the
memory read and write pointers. The Transmit Data Storage receives data from the microprocessor interface, and
stores the data in memory. The Transmit Trace ID Processor reads the data from the Transmit Data Storage. The
Transmit Data Storage contains the transmit trail trace identifier. Note: The contents of the transmit trail (path) trace
identifier memory will be random data immediately after power-up, and will not change during a reset (RST or DRST
low).
Programmable trail trace ID – The trail trace ID controller can be programmed to handle a 16-byte trail trace
identifier (trail trace mode).
Programmable transmit trace ID – All sixteen bytes of the transmit trail trace identifier are programmable.
Programmable receive expected trace ID – A 16-byte expected trail trace identifier can be programmed.
Both a mismatch and unstable indication are provided.
Programmable trace ID multiframe alignment – The transmit side can be programmed to perform trail trace
multiframe alignment insertion. The receive side can be programmed to perform trail trace multiframe
synchronization.
Programmable bit reordering – The trace identifier data can be output MSB first or LSB first from the data
storage.
Programmable data inversion – The trace identifier data can be inverted immediately after trace ID
processing on the transmit side, and immediately before trail ID processing on the receive side.
Fully independent transmit and receive sides
Fully independent Line side and register interface timing – The data storage can be read from or written to
via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to
via the line side while all microprocessor interface clocks and signals are inactive.
Adapter
Clock
Rate
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
Transmit
Framer
DS3 / E3
Receive
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
FRAC/
PLCP
TX
RX FRAC/
PLCP
Processor
Processor
Processor
Processor
TX BERT
RX BERT
Tx Packet
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
FIFO
Tx
FIFO
Rx