DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 59

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BSWAP
WIDTH
A[10:1]
MODE
GPIO1
A[0] /
WR /
RDY
ALE
RD /
R/W
PIN
INT
CS
DS
TYPE
I/O
Oz
Oz
I
I
I
I
I
I
I
outputs during register reads. The upper 8 bits are not used and never driven in 8-bit
bus mode.
Weak pullup resistors or bus holders should be used for each pin.
Address bus (minus LSB)
A[10:1]: identifies the specific 16 bit registers, or group of 8 bit registers, being
accessed. A[10] must be tied to ground for the DS3161 and DS3162 versions.
Address bus LSB / Byte Swap
A[0]: This signal is connected to the lower address bit in 8-bit systems. (WIDTH=0)
BSWAP: This signal is tied high or low in 16-bit systems.
(WIDTH=1)
Address Latch Enable
ALE: This signal is used to latch the address on the A[10:0] pins in multiplexed
address systems. When it is high the address is fed through the address latch to the
internal logic. When it transitions to low, the address is latched and held internally
until the signal goes back high. ALE should be tied high for non-multiplexed address
systems.
Chip Select (active low)
CS: This signal must be low during all accesses to the registers
Read Strobe (active low) / Data Strobe (active low)
RD: Read Strobe mode (MODE=0):
DS: Data Strobe mode (MODE=1):
Write Strobe (active low) / R/W Select
WR: Write Strobe mode (MODE=0):
R/W: Data Strobe mode (MODE=1):
Ready handshake (active low)
RDY: This ready signal is driven low when the current read or write cycle is in
progress. When the current read or write cycle is not ready it is driven high. When
device is not selected, it is not driven.
Interrupt (active low)
This signal is tri-state when RST pin is low.
INT: This interrupt signal is driven low when an event is detected on any of the
enabled interrupt sources in any of the register banks. When there are no active and
enabled interrupt sources, the pin can be programmed to either drive high or not drive
high. The reset default is to not drive high when there are no active and enabled
interrupt source. All interrupt sources are disabled when RST=0 and they must be
programmed to be enabled.
Mode select RD/WR or DS strobe mode
MODE: 1 = Data Strobe Mode, 0 = Read/Write Strobe Mode
Data bus width select 8 or 16-bit interface
WIDTH: 1 = 16-bits, 0 = 8 bits
General-Purpose I/O 1
GPIO1: This signal is configured to be a general-purpose I/O pin, or an alarm output
signal for port 1.
1 = Output register bits 15:8 on D[7:0], D[15:8] not driven
0 = Output register bits 7:0 on D[7:0], D[15:8] not driven
1 = Output register bits 15:8 on D[7:0], 7:0 on D[15:8]
0 = Output register bits 7:0 on D[7:0], 15:8 on D[15:8]
RD is low during a register read.
DS is low during either a register read or a write.
WR is low during a register write.
R/W is high during a register read cycle, and low during a register write cycle.
MISC I/O
FUNCTION