DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 307

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3163N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Transmit F1 Byte (TF1[7:0]) – These eight bits are the F1 byte to be inserted into the transmit PLCP
frame.
Bits 7 to 4: Transmit REI Setting (TREI[3:0]) – When automatic REI generation is defeated (PLCP.TCR.AREID =
0), these bits are inserted into the REI bits (G1[1:4]).
Bit 3: Transmit RAI Setting (TRAI) –This bit is inserted into the RAI bits (G1[5]).
Bits 2 to 0: Transmit Link Status Signal (TLSS[2:0]) – These three bits are the transmit link status signal
(G1[6:8]) to be inserted into the transmit PLCP frame.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Transmit M2 Byte (TM2[7:0]) – These eight bits are the M2 byte to be inserted into the transmit
PLCP frame.
Bits 7 to 0: Transmit M1 Byte (TM1[7:0]) – These eight bits are the M1 byte to be inserted into the transmit PLCP
frame.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Transmit Z2 Byte (TZ2[7:0]) – These eight bits are the Z2 byte to be inserted into the transmit PLCP
frame.
Bits 7 to 0: Transmit Z1 Byte (TZ1[7:0]) – These eight bits are the Z1 byte to be inserted into the transmit PLCP
frame.
TREI3
TM27
TM17
TF17
TZ27
TZ17
15
15
15
0
7
0
0
7
0
0
7
0
TREI2
TM26
TM16
TF16
TZ26
TZ16
14
14
14
0
6
0
0
6
0
0
6
0
PLCP.TFGBR
PLCP Transmit F1 and G1 Byte Register
(1,3,5,7)54h
PLCP.TM12BR
PLCP Transmit M1 and M2 Byte Register
(1,3,5,7)56h
PLCP.TZ12BR
PLCP Transmit Z1 and Z2 Byte Register
(1,3,5,7)58h
TREI1
TM25
TM15
TF15
TZ25
TZ15
13
13
13
0
5
0
0
5
0
0
5
0
TREI0
TM24
TM14
TF14
TZ24
TZ14
12
12
12
0
0
0
0
0
4
4
4
0
TM23
TM13
TF13
TZ23
TZ13
TRAI
11
11
11
0
3
0
0
3
0
0
3
0
TLSS2
TM22
TM12
TF12
TZ22
TZ12
10
10
10
0
2
0
0
2
0
0
2
0
TLSS1
TM21
TM11
TF11
TZ21
TZ11
9
0
1
0
9
0
1
0
9
0
1
0
TLSS0
TM20
TM10
TF10
TZ20
TZ10
8
0
0
0
8
0
0
0
8
0
0
0

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