DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 33

IC TRPL ATM/PACKET PHY 400-PBGA

DS3163

Manufacturer Part Number
DS3163
Description
IC TRPL ATM/PACKET PHY 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3163

Applications
*
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3163
Manufacturer:
Maxim Integrated
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6.8 Clear-Channel ATM/Packet Mode
The Clear-Channel ATM/Packet Mode maps/de-maps ATM cells or HDLC packets into/from a serial datastream,
bypassing the DS3/E3 formatter/framer. Major functional blocks for the Clear-Channel ATM/Packet Mode are
shown in
Table 6-8. Clear-Channel ATM/Packet Mode Configuration Modes
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-8. Clear-Channel ATM/Packet Modes
MODE
Figure
TOHMIn
RLCLKn
RNEGn/
ROHMIn
TPOSn/
TNEGn/
TLCLKn
RLCVn/
RPOSn/
RDATn
TDATn
6-8. Mapping configuration is programmable on per port basis and is shown in
Clock Rate
Adapter
1XX0X0
1XX0X0
1XX0X0
1XX0X0
1XX0X0
1XX0X0
FM[5:0]
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
00
01
10
11
10
11
SIM[1:0]
GL.CR1
IEEE P1149.1
JTAG Test
Access Port
X
X
1
1
0
0
PORT.CR2
PMCPE
GEN
UA1
Rx Packet
Processor
Processor
RX BERT
Processor
Processor
Tx Packet
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx
n = port # (1-4)
Table
6-8.

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