DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 2

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FEATURES (continued)
DETAILED DESCRIPTION
The DS3161 (single), DS3162 (dual), DS3163 (triple), and DS3164 (quad) PHYs perform all the functions
necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3
(34.368Mbps) framed, or 52Mbps clear-channel data streams. Dedicated cell processor and packet processor
blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in
DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or
G.832 E3 data streams. PLCP framers provide legacy ATM transmission-convergence
performed for clear-channel ATM cell
DS316x DS3/E3 ATM/Packet PHYs provide system-on-chip solutions (from DS3/E3/STS-1 digital lines to
ATM/Packet UTOPIA/POS-PHY Level 2/3 system switch) for universal high-density line cards in the unchannelized
DS3/E3/clear-channel DS3 ATM/Packet applications. Unused functions can be powered down to reduce device
power. The DS316x ATM/Packet PHYs with embedded framers conform to the telecommunications standards
listed in Section
1 BLOCK DIAGRAM
Figure 1-1
Figure 1-1. DS316x Functional Block Diagram
Full-Featured DS3/E3/PLCP Alarm Generation
and Detection
Built-In HDLC Controllers with 256-Byte FIFOs
for Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes and PLCP NR/GC
Bytes
On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis
TOHMOn/
RLCLKn
RPOSn/
RNEGn/
ROHMIn
TNEGn/
TLCLKn
shows the functional block diagram of one channel ATM/Packet PHY.
TPOSn/
RLCVn/
RDATn
TDATn
4.
Adapter
Clock
DS316x
Rate
Encoder
Decoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
support.
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
Transmit
Receive
Framer
DS3 / E3
Formatter
Buffer
Trace
Trail
With integrated hardware support for both cells and packets, the
HDLC
GEN
UA1
2
FRAC/
PLCP
TX
RX FRAC/
PLCP
Large Performance-Monitoring Counters for
Accumulation Intervals of at Least 1 Second
Flexible Overhead Insertion/Extraction Ports for
DS3, E3, and PLCP Framers
Pin and Software Compatible with DS3181–
DS3184 Single–Quad ATM/Packet PHYs with
Built-In LIUs and DS3171–DS3174 Single–Quad
DS3/E3 Single-Chip Transceivers—Framers and
LIUs
Processor
Processor
Processor
TX BERT
RX BERT
Processor
Tx Packet
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
FIFO
Tx
FIFO
Rx
support.
n = port #
DSS scrambling is
TSOX
TSPA
TEOP
TSX
TMOD[1:0]
TERR
/RSX
RDXA[4:2]
RSOX
REOP
TSCLK
TADR[4:0]
TDATA[31:0]
TPRTY
TDXA[4:2]
TDXA[1]/TPXA
RSCLK
RADR[4:0]
RDATA[31:0]
RPRTY
REN
RVAL
RMOD[1:0]
RERR
TEN