DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 156

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.9 Fractional Payload Controller
10.9.1 General Description
The Fractional Payload Controller allows the user to utilize a fraction of the DS3/E3 payload for ATM cell or HDLC
packets. The unused DS3/E3 payload is considered fractional overhead and can be used as a proprietary data
link. The allocation given to the fractional payload is programmable controlled using internal counters or controlled
externally. The fractional overhead data can optionally be programmed to transmit all 0’s, all 1’s, a 1010 pattern, or
insert data from an external source.
The Fractional Payload Controller de-maps fractional payload and overhead data from the DS3/E3 payload in the
receive direction and maps fractional payload and overhead data into the DS3/E3 payload in the transmit direction.
The receive direction extracts the fractional payload and fractional overhead data bits from the receive DS3/E3
payload, performs fractional payload/overhead data demultiplexing, sends the fractional payload to the ATM/packet
processor, and sends the fractional overhead data to an external interface.
The transmit direction accepts the fractional overhead from an internal register or the external interface and
fractional payload data from the ATM/packet processor, performs fractional overhead/payload data multiplexing,
and inserts the fractional overhead and payload data into the transmit DS3/E3 payload.
See
Figure 10-34. Fractional Payload Controller Detailed Block Diagram
10.9.2 Features
•
•
•
Programmable payload allocation – The payload data and fractional overhead allocation can be
programmed via registers.
Externally controlled payload allocation – The payload data and fractional overhead allocation can be
controlled by an external source via pins.
Fractional overhead extraction and insertion – Extracts all fractional overhead from the DS3/E3 payload
and sends it to an external serial interface. Inserts all fractional overhead from a serial interface and into the
transmit DS3/E3 payload. Optionally, the transmit fractional overhead can be set to insert all 0’s, all 1’s, or a
1010 pattern.
Adapter
Figure 10-34
Clock
Rate
for the location of the Fractional Payload Controller in the DS316x devices.
Decoder
Encoder
B3ZS/
HDB3
HDB3
B3ZS/
TUA1
TAIS
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
Transmit
Framer
DS3 / E3
Receive
Formatter
Buffer
Trace
Trail
HDLC
GEN
UA1
FRAC/
PLCP
TX
RX FRAC/
PLCP
Processor
Processor
Processor
RX BERT
Processor
Tx Packet
TX BERT
Packet
Tx Cell
Microprocessor
Cell
Rx
Rx
Interface
FIFO
Tx
Rx
FIFO