DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 141

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-28. Cell Format for 52-Byte Cell With 32-Bit Data Bus
10.7.6 Packet Processor
10.7.6.1 Transmit Packet Processor
The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing,
packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The
data output from the Transmit Packet Processor can be either a serial data stream (bit synchronous mode) or an 8-
bit parallel data stream (octet-aligned mode). The type of data stream output from the Transmit Packet Processor
affects stuffing, abort insertion, inter-octet padding, inter-frame padding, and packet scrambling, however, it does
not affect bit reordering, FCS processing, or packet error insertion. Packet processing can be disabled (clear-
channel enable). Disabling packet processing disables FCS processing, packet error insertion, stuffing, packet
abort sequence insertion, and inter-frame padding. Only bit reordering and packet scrambling are not disabled.
When packet processing is disabled, data is continually read out of the Transmit FIFO. When the Transmit FIFO is
read empty, the output data stream will be padded with FFh until the Transmit FIFO contains more data than the
"almost empty" level. The 32-bit data words read from the Transmit FIFO are multiplexed into an 8-bit parallel data
stream and passed on to bit reordering.
Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream
DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB
is in DT[7] of the outgoing data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit transmitted. If packet
processing is disabled the data stream is passed on to packet scrambling, bypassing FCS processing, packet error
insertion, stuffing, packet abort sequence insertion, and inter-frame padding. If packet processing is disabled in bit
synchronous mode, the serial data stream is demultiplexed in to an 8-bit data stream before being passed on.
FCS processing calculates an FCS and appends it to the packet. FCS calculation is a CRC-16 or CRC-32
calculation over the entire packet. The polynomial used for FCS-16 is x
FCS-32 is x
calculation. The FCS type is programmable. If FCS append is enabled, the calculated FCS is appended to the
packet. If FCS append is disabled, the packet is transmitted without an FCS. The FCS append mode is
programmable. If packet processing is disabled, FCS processing is not performed.
Packet error insertion inserts errors into the FCS bytes. A single FCS bit is corrupted in each errored packet. The
FCS bit corrupted is changed from errored packet to errored packet. Error insertion can be controlled by a register
or by the manual error insertion input (TMEI). The error insertion initiation type (register or input) is programmable.
If a register controls error insertion, the number and frequency of the errors are programmable. If FCS append is
disabled, packet error insertion will not be performed. If packet processing is disabled, packet error insertion is not
performed.
Stuffing inserts control data into the packet to prevent packet data from mimicking flags. Stuffing is performed from
the beginning of a packet until the end of a packet. In bit synchronous mode, the 8-bit parallel data stream is
multiplexed into a serial data stream, and bit stuffing is performed. Bit stuffing consists of inserting a '0' directly
following any five contiguous '1's. In octet-aligned mode, byte stuffing is performed. Byte stuffing consists of
Bit 31
32
Payload 41
Payload 45
Payload 1
Payload 5
Header 1
+ x
•
•
•
26
+ x
23
+ x
22
Payload 42
Payload 46
+ x
Payload 2
Payload 6
Header 2
16
•
•
•
+ x
12
+ x
11
+ x
Payload 43
Payload 47
Payload 3
Payload 7
10
Header 3
+ x
•
•
•
8
+ x
7
+ x
5
+ x
Payload 44
Payload 48
Payload 4
Payload 8
Header 4
16
4
+ x
+ x
•
•
•
12
2
Bit 0
+ x + 1. The FCS is inverted after
+ x
5
+ 1. The polynomial used for
12
13
2
3
1
nd
rd
st
th
th
Transfer
Transfer
Transfer
Transfer
Transfer