DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 106

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-5. CLAD Block
The clock rate adapter can also be disabled and all three clocks supplied externally using the CLKA, CLKB and
CLKC pins as clock inputs. When the CLAD is disabled, the three reference clocks DS3, E3 and STS-1 will need to
be applied to the CLKA, CLKB and CLKC pins, respectively. If any of the three frequencies is not required, it does
not need to be applied to the CLAD CLK pins.
The CLAD MODE inputs to the clock rate adapter are composed of CLAD[3:0] control bits (located in the
Register) which determines which pins are input and output and which clock rate is on which pin. When
CLAD[3:0]=00XX, the PLL circuits are disabled and the signals on the input clock pins are used.
CLAD[3:0]=(01XX or 10XX or 11XX), none, one or two PLL circuits are enabled to generate the required clocks as
determined by the CLAD[3:0] bits and the framing mode (FM[5:0]) and the line mode (LM) control bits. If a clock
rate is not required on the CLAD output clock pins, then the PLL used to generate that clock is disabled and
powered down.
For example, in a design that only has the ports running at DS3 rates, then CLAD[3:0] can be set = 0100 and no
PLL circuit will be enabled.
CLKC
CLKA
CLKB
CLAD MODE
CLAD
DS3 clock
E3 clock
CC52 clock
GL.CR2
When