DS3163 Maxim Integrated Products, DS3163 Datasheet - Page 79

• Manufacturer Part Number: DS3163
• Description: IC TRPL ATM/PACKET PHY 400-PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3163

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-33
the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it has a
complete cell ready for transfer by asserting RPXA. On clock edge 5, the ATM device selects PHY port 'N'. On
clock edge 6, the ATM device indicates to PHY port 'N' that it is ready to accept a complete cell transfer by
asserting REN. On clock edge 8, PHY port 'N' starts a cell transfer by placing the first byte of cell data on RDATA,
and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 9, PHY port 'N' de-asserts
RSOX as it continues to place additional bytes of the cell on RDAT. On clock edge 11, the ATM device polls PHY
device 'N'. On clock edge 12, PHY port 'M' indicates to the ATM device that it has a complete cell ready for transfer
by asserting RPXA. On clock edge 12, PHY port 'N' indicates to the ATM device that it does not have a complete
cell ready for transfer by de-asserting RPXA. On clock edge 15, the ATM device deselects PHY port 'N' and selects
PHY port 'M' by de-asserting REN and placing PHY port 'M's address on RADR. On clock edge 16, the ATM device
asserts REN. On clock edge 17, PHY port 'N' stops transferring cell data. On clock edge 18, PHY port 'M' starts a
cell transfer by placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first
byte of the cell. On clock edge 19, PHY port 'M' de-asserts RSOX as it continues to place additional bytes of the
cell on RDATA.
Figure 8-33. UTOPIA Level 3 Receive Multiple Cell Transfer Polled Mode
Cell From:
Transfer
RADR
RSOX
RPXA
RDAT
RCLK
REN
shows a multi-port receive interface multiple cell transfer from different PHY ports. On clock edge 1,
M
K
X
1
N
X
L
2
M
O
X
3
N
X
P
4
Q
O
X
5
N
X
P
6
R
Q
X
7
N
X
J
8
H1
K
R
9
H2
L
J
10
…
…
…
11
P43
N
L
12
N
P44
M
O
13
P45
N
P
14
P46
Q
O
15
P47
M
P
16
P48
R
Q
17
M
X
J
18
H1
K
R
19
M
H2
L
J
20
P1
M
K